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References: <20220510060440.67178-1-jiapeng.chong@linux.alibaba.com>
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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Tue, 10 May 2022 11:09:15 -0400
Message-ID: <CADnq5_NxH5WzL6=5ZG2Cb0CBPU3FwP7ZS2ZMzyYHZ00XKe3E5w@mail.gmail.com>
Subject: Re: [PATCH] drm/amdgpu: clean up some inconsistent indenting
To:     Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Cc:     "Deucher, Alexander" <alexander.deucher@amd.com>,
        Dave Airlie <airlied@linux.ie>,
        xinhui pan <Xinhui.Pan@amd.com>,
        Abaci Robot <abaci@linux.alibaba.com>,
        LKML <linux-kernel@vger.kernel.org>,
        Maling list - DRI developers 
        <dri-devel@lists.freedesktop.org>,
        amd-gfx list <amd-gfx@lists.freedesktop.org>,
        Christian Koenig <christian.koenig@amd.com>
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Precedence: bulk

Applied.  Thanks!

Alex

On Tue, May 10, 2022 at 2:05 AM Jiapeng Chong
<jiapeng.chong@linux.alibaba.com> wrote:
>
> Eliminate the follow smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c:35 nbio_v7_7_get_rev_id() warn:
> inconsistent indenting.
>
> drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c:214 nbio_v7_7_init_registers()
> warn: inconsistent indenting.
>
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 17 ++++++++---------
>  1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
> index e32c874b42b5..cdc0c9779848 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
> @@ -32,8 +32,7 @@ static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
>  {
>         u32 tmp;
>
> -               tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
> -
> +       tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
>         tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
>         tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
>
> @@ -211,14 +210,14 @@ static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
>  {
>         uint32_t def, data;
>
> -               def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
> -               data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
> -                       CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> -               data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
> -                       CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
> +       def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
> +       data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
> +                            CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> +       data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
> +                            CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
>
> -               if (def != data)
> -                       WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
> +       if (def != data)
> +               WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
>
>  }
>
> --
> 2.20.1.7.g153144c
>