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From:   "Michael Kelley (LINUX)" <mikelley@microsoft.com>
To:     Jeffrey Hugo <quic_jhugo@quicinc.com>,
        KY Srinivasan <kys@microsoft.com>,
        Haiyang Zhang <haiyangz@microsoft.com>,
        Stephen Hemminger <sthemmin@microsoft.com>,
        "wei.liu@kernel.org" <wei.liu@kernel.org>,
        Dexuan Cui <decui@microsoft.com>,
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        "robh@kernel.org" <robh@kernel.org>, "kw@linux.com" <kw@linux.com>,
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CC:     Jake Oshins <jakeo@microsoft.com>,
        David Zhang <dazhan@microsoft.com>,
        "linux-hyperv@vger.kernel.org" <linux-hyperv@vger.kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 0/2] hyperv compose_msi_msg fixups
Thread-Topic: [PATCH 0/2] hyperv compose_msi_msg fixups
Thread-Index: AQHYY+7pzPi4deY6dEe1T1/467S4HK0YaiIA
Date:   Tue, 10 May 2022 18:13:33 +0000
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From: Jeffrey Hugo <quic_jhugo@quicinc.com> Sent: Monday, May 9, 2022 2:48 =
PM
>=20
> While multi-MSI appears to work with pci-hyperv.c, there was a concern ab=
out
> how linux was doing the ITRE allocations.  Patch 2 addresses the concern.
>=20
> However, patch 2 exposed an issue with how compose_msi_msg() was freeing =
a
> previous allocation when called for the Nth time.  Imagine a driver using
> pci_alloc_irq_vectors() to request 32 MSIs.  This would cause compose_msi=
_msg()
> to be called 32 times, once for each MSI.  With patch 2, MSI0 would alloc=
ate
> the ITREs needed, and MSI1-31 would use the cached information.  Then the=
 driver
> uses request_irq() on MSI1-17.  This would call compose_msi_msg() again o=
n those
> MSIs, which would again use the cached information.  Then unmask() would =
be
> called to retarget the MSIs to the right VCPU vectors.  Finally, the driv=
er
> calls request_irq() on MSI0.  This would call conpose_msi_msg(), which wo=
uld
> free the block of 32 MSIs, and allocate a new block.  This would undo the
> retarget of MSI1-17, and likely leave those MSIs targeting invalid VCPU v=
ectors.
> This is addressed by patch 1, which is introduced first to prevent a regr=
ession.
>=20
> Jeffrey Hugo (2):
>   PCI: hv: Reuse existing ITRE allocation in compose_msi_msg()
>   PCI: hv: Fix interrupt mapping for multi-MSI
>=20
>  drivers/pci/controller/pci-hyperv.c | 76 ++++++++++++++++++++++++++++---=
------
>  1 file changed, 59 insertions(+), 17 deletions(-)
>=20
> --
> 2.7.4

I tested these two patches in combination with the earlier two on
5.18-rc6 in an ARM64 VM in Azure.   This was a smoke-test to ensure
everything compiled and that the changes aren't fundamentally broken
on ARM64.   The PCI device in this case is the Mellanox Virtual Function
offered to VMs in Azure, which is MSI-X.   As such, the new MSI "batch"
handling is not tested.

Tested-by: Michael Kelley <mikelley@microsoft.com>