Received: by 2002:a6b:500f:0:0:0:0:0 with SMTP id e15csp6243211iob; Tue, 10 May 2022 13:46:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8omasBpV4ovZSYT28cjUDYjOkOEliENpYR8dMkjiHxNgV4QfIC/JkBBzUd3SrxOeLgoHn X-Received: by 2002:a05:6402:2547:b0:428:1dd3:2751 with SMTP id l7-20020a056402254700b004281dd32751mr24857357edb.87.1652215610785; Tue, 10 May 2022 13:46:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1652215610; cv=none; d=google.com; s=arc-20160816; b=Jn/WIu785QNtQ/YAJRfK2NgM3aZ9xemEHGhXtlfGVdHEP7aOutJ//tXx8uqHSm9Hve xYhgi4OxqCm1BkIwTE4zrf8VJ8+ScJf1fN4+OxzX54tuOIUIENlA3EUq8e0/Fc2GjjOU czwl1DiA8Xv6tHObVY+t4tLE3fgLO00a/CPNbzQplwU3CY/+xrM5smNxmOpboPKP1p3r onqYpf29T13WdebVKpqEkfhBU/vqPnqAiRxEa1tH9SnjXwQfeFgiSKAF+ONTU3G6CHwm rqGsNUsoBs376chSYv0rzzeUhEtBDVWTbu2m2YTWxzVtizP75c+EDn19ekSbeZnBDZd3 p4cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uPrPcU0NNRfcytiymJ5newNh/y09rPMpUHjI3XfPt0A=; b=AdHeDEXUugPYNqfA1RcE+/7QfrWHJU4W8l3wmm7XArlDTZs6EtMhVFhbcYNUmHugNc 3EVM3z0u71PLEQR6xJqLHdqo5WTwOCQYm4K6vFria4slteKiVLsLFhWlyxUlEV0zZQUm B98Hv4ocePFjpS7a0hbaGZhGhYaJvdlHwCOO/wcTNZVvyzzVbUq/y5UsWh9ky7CikSIi oO0k7+l7Hv4vPS0snoezfqIa3VxDMUWcmn6UrRZszRFhgkpYpapf/agBy6YQKlsy6VNg OOlvFOXB3uJrzcmJSAkbsH+9kyliOQGF+rHbHAUHPCaGDdfJu8UZu7EaQxs8p24xOfJW hMFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=0dkWpJiv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i13-20020a1709064fcd00b006e7cd47a2d3si473718ejw.189.2022.05.10.13.46.27; Tue, 10 May 2022 13:46:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=0dkWpJiv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243941AbiEJOUD (ORCPT + 99 others); Tue, 10 May 2022 10:20:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245135AbiEJNrZ (ORCPT ); Tue, 10 May 2022 09:47:25 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3AC32BD0FE; Tue, 10 May 2022 06:35:24 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 04C74618CB; Tue, 10 May 2022 13:35:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E435C385A6; Tue, 10 May 2022 13:35:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1652189723; bh=9KXUXSha3Y6rK9qQFOv8v7ZmdqGgVVa0hwz5xEg1kj4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0dkWpJivaT5I3dmjNJgv28mcufXjGE9Nd3J/r3EnqD34xu9wyMHQwUUnMEODgtUtO gy71z8jZI5gwc3Y+YsE8i+uRm51uKEYsTDHagnYUBDnepIS5HdZiHoJG4I838rDNch yl8AmtNeoUXyNZDpxeDXY+cznlHsUK8ZhZtKCS/s= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, pali@kernel.org, =?UTF-8?q?Marek=20Beh=FAn?= , Lorenzo Pieralisi Subject: [PATCH 5.15 124/135] PCI: aardvark: Add support for masking MSI interrupts Date: Tue, 10 May 2022 15:08:26 +0200 Message-Id: <20220510130743.954315129@linuxfoundation.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220510130740.392653815@linuxfoundation.org> References: <20220510130740.392653815@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Roh?r commit e77d9c90691071769cd2b86ef097f7d07167dc3b upstream. We should not unmask MSIs at setup, but only when kernel asks for them to be unmasked. At setup, mask all MSIs, and implement IRQ chip callbacks for masking and unmasking particular MSIs. Link: https://lore.kernel.org/r/20220110015018.26359-11-kabel@kernel.org Signed-off-by: Pali Roh?r Signed-off-by: Marek Beh?n Signed-off-by: Lorenzo Pieralisi Signed-off-by: Marek Beh?n Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pci-aardvark.c | 54 ++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 5 deletions(-) --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -274,6 +274,7 @@ struct advk_pcie { raw_spinlock_t irq_lock; struct irq_domain *msi_domain; struct irq_domain *msi_inner_domain; + raw_spinlock_t msi_irq_lock; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; u16 msi_msg; @@ -570,12 +571,10 @@ static void advk_pcie_setup_hw(struct ad advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); - /* Disable All ISR0/1 Sources */ + /* Disable All ISR0/1 and MSI Sources */ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); - - /* Unmask all MSIs */ - advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); + advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); /* Unmask summary MSI interrupt */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); @@ -1193,10 +1192,52 @@ static int advk_msi_set_affinity(struct return -EINVAL; } +static void advk_msi_irq_mask(struct irq_data *d) +{ + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned long flags; + u32 mask; + + raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); + mask = advk_readl(pcie, PCIE_MSI_MASK_REG); + mask |= BIT(hwirq); + advk_writel(pcie, mask, PCIE_MSI_MASK_REG); + raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); +} + +static void advk_msi_irq_unmask(struct irq_data *d) +{ + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned long flags; + u32 mask; + + raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); + mask = advk_readl(pcie, PCIE_MSI_MASK_REG); + mask &= ~BIT(hwirq); + advk_writel(pcie, mask, PCIE_MSI_MASK_REG); + raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); +} + +static void advk_msi_top_irq_mask(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void advk_msi_top_irq_unmask(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + static struct irq_chip advk_msi_bottom_irq_chip = { .name = "MSI", .irq_compose_msi_msg = advk_msi_irq_compose_msi_msg, .irq_set_affinity = advk_msi_set_affinity, + .irq_mask = advk_msi_irq_mask, + .irq_unmask = advk_msi_irq_unmask, }; static int advk_msi_irq_domain_alloc(struct irq_domain *domain, @@ -1286,7 +1327,9 @@ static const struct irq_domain_ops advk_ }; static struct irq_chip advk_msi_irq_chip = { - .name = "advk-MSI", + .name = "advk-MSI", + .irq_mask = advk_msi_top_irq_mask, + .irq_unmask = advk_msi_top_irq_unmask, }; static struct msi_domain_info advk_msi_domain_info = { @@ -1300,6 +1343,7 @@ static int advk_pcie_init_msi_irq_domain struct device *dev = &pcie->pdev->dev; phys_addr_t msi_msg_phys; + raw_spin_lock_init(&pcie->msi_irq_lock); mutex_init(&pcie->msi_used_lock); msi_msg_phys = virt_to_phys(&pcie->msi_msg);