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Message-ID: <e740f0f7-8010-a390-98e0-d549d981f5e3@quicinc.com>
Date:   Thu, 12 May 2022 12:51:48 +0530
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Subject: Re: [PATCH] arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs
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To:     Sai Prakash Ranjan <quic_saipraka@quicinc.com>,
        Will Deacon <will@kernel.org>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Marc Zyngier <maz@kernel.org>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Mark Rutland <mark.rutland@arm.com>
CC:     Andre Przywara <andre.przywara@arm.com>,
        <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-arm-msm@vger.kernel.org>,
        Jeffrey Hugo <quic_jhugo@quicinc.com>,
        Rajendra Nayak <quic_rjendra@quicinc.com>,
        Prasanna Kumar <quic_kprasan@quicinc.com>
References: <20220511080247.1530-1-quic_shrekk@quicinc.com>
 <7a7b4657-ec75-7984-1a6e-50ff928ab09c@quicinc.com>
From:   Shreyas K K <quic_shrekk@quicinc.com>
In-Reply-To: <7a7b4657-ec75-7984-1a6e-50ff928ab09c@quicinc.com>
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Hi Sai,

On 5/11/2022 4:43 PM, Sai Prakash Ranjan wrote:
> Hi Shreyas,
>
> On 5/11/2022 1:32 PM, Shreyas K K wrote:
>> Add KRYO4XX gold/big cores to the list of CPUs that need the
>> repeat TLBI workaround. Apply this to the affected
>> KRYO4XX cores (rcpe to rdpe).
>>
>> The variant and revision bits are implementation defined and are
>> different from the their Cortex CPU counterparts on which they are
>> based on, i.e., (r0p0 to r1p0) is equivalent to (rcpe to rdpe).
>>
>> Signed-off-by: Shreyas K K <quic_shrekk@quicinc.com>
>> ---
>>   Documentation/arm64/silicon-errata.rst | 3 +++
>>   arch/arm64/kernel/cpu_errata.c         | 2 ++
>>   2 files changed, 5 insertions(+)
>>
>> diff --git a/Documentation/arm64/silicon-errata.rst 
>> b/Documentation/arm64/silicon-errata.rst
>> index 466cb9e89047..d27db84d585e 100644
>> --- a/Documentation/arm64/silicon-errata.rst
>> +++ b/Documentation/arm64/silicon-errata.rst
>> @@ -189,6 +189,9 @@ stable kernels.
>> +----------------+-----------------+-----------------+-----------------------------+
>>   | Qualcomm Tech. | Kryo4xx Silver  | N/A             | 
>> ARM64_ERRATUM_1024718       |
>> +----------------+-----------------+-----------------+-----------------------------+
>> +| Qualcomm Tech. | Kryo4xx Gold    | N/A             | 
>> ARM64_ERRATUM_1286807       |
>> ++----------------+-----------------+-----------------+-----------------------------+ 
>>
>> +
>> +----------------+-----------------+-----------------+-----------------------------+
>>   | Fujitsu        | A64FX           | E#010001        | 
>> FUJITSU_ERRATUM_010001      |
>> +----------------+-----------------+-----------------+-----------------------------+
>> diff --git a/arch/arm64/kernel/cpu_errata.c 
>> b/arch/arm64/kernel/cpu_errata.c
>> index 4c9b5b4b7a0b..2518657e6de1 100644
>> --- a/arch/arm64/kernel/cpu_errata.c
>> +++ b/arch/arm64/kernel/cpu_errata.c
>> @@ -208,6 +208,8 @@ static const struct arm64_cpu_capabilities 
>> arm64_repeat_tlbi_list[] = {
>>   #ifdef CONFIG_ARM64_ERRATUM_1286807
>>       {
>>           ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
>> +        /* Kryo4xx Gold (rcpe to rdpe) => (r0p0 to r1p0) */
>> +        ERRATA_MIDR_RANGE(QCOM_CPU_PART_KRYO_4XX_GOLD, 0xc, 0xe, 
>> 0xd, 0xe),
>>       },
>>   #endif
>>       {},
>
> Why not include r2p0 and r3p0 which are affected by this erratum? I 
> see these revisions are present
> in our SoCs as per the document.
>
> Thanks,
> Sai

Acknowledged. Changing in the next version.

Thanks,
Shreyas