Received: by 2002:a6b:500f:0:0:0:0:0 with SMTP id e15csp59551iob; Thu, 12 May 2022 18:30:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzkQh/byYGf5yLpsHjQmjGY0Xc6VhlUXGAq8mP+/RPL0AnRi/BpfmRCt623kiNDBL+d2kIx X-Received: by 2002:a05:6402:40cf:b0:427:cead:dca with SMTP id z15-20020a05640240cf00b00427cead0dcamr38405285edb.380.1652405435630; Thu, 12 May 2022 18:30:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1652405435; cv=none; d=google.com; s=arc-20160816; b=VaXSHD6ivc7fol0qpVclhqhKuT1avTioDu4dPaeL33DN5xL0cDbB/4Iy0l/BQF+kwS d/Dr4VVKAqFg/EheuMWnbLInhEK8e42Qbt21OoerS+5a8iG3gUuIM39DN94CTU8FHxaG p7cjDN5GsDPhVn3dpbHr1IlLyLGPJzE9wNI+/lVT/BHCkLxYO1ysl6X61eVJ2sJksw1M AtCyqxBXVc5LcEOohCVwoFfCVibQdVsAYaKEJRF4eJo2NlTBOSAwVAJZ9FtCVtI+TPPT uVkKEpFUPezD1vBL2YBqAXRom0mHR7cIisC2E7WPurYjeWkHl9XifdJz67pK/6O5GPMb Pu9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=xoYOHfPmi7SK5UVEFEe+9orN0sDaVSbnE3WoQkYKbxk=; b=A8VD1wD/M1LtMA3jwR7upwqYjHK3AmRXWXqg3CcohnEVYGsJ0Kx3yScIT0FstCihP9 hO3fLiUs7tTeOi1WqtF7icCmnH0MbVPddTNmv5vVNQre8XzgOMp2AzgYBO6LuEIYc9ZC 1jDZuMWUiHjQ+yVwaow2UcGFzozyrT5w03djJtXrvuvH/i43Yr4r4z7PR0G457lBnk4z q67YeHkAW92p56GcmI0onwQcWIPExKyM55bjeubroe+zlu5UkSnHT+jwNj2PKHmfMN6c 9hrwPuGZMxpXWsZj4DDBXKgHQ3NB5orpdw1SCea5f2M2dswvilFcFDi6GTtpeBNXv0kc WiOw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k14-20020aa7c04e000000b00425c9955318si630795edo.345.2022.05.12.18.30.10; Thu, 12 May 2022 18:30:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354166AbiELNHi (ORCPT + 99 others); Thu, 12 May 2022 09:07:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354145AbiELNHa (ORCPT ); Thu, 12 May 2022 09:07:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1C396A056; Thu, 12 May 2022 06:07:27 -0700 (PDT) X-UUID: 05ad02d4eb2f4db88892bbad673c9638-20220512 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:971b4917-5d07-4918-be27-f29d648cfd5a,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:25 X-CID-META: VersionHash:faefae9,CLOUDID:1b12fdf1-ab23-4aed-a67b-f96514452486,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 05ad02d4eb2f4db88892bbad673c9638-20220512 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 325103861; Thu, 12 May 2022 21:07:21 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 12 May 2022 21:07:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 May 2022 21:07:19 +0800 From: Johnson Wang To: , , , CC: , , , , , , , , Johnson Wang Subject: [PATCH v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings Date: Thu, 12 May 2022 21:07:14 +0800 Message-ID: <20220512130715.8165-2-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220512130715.8165-1-johnson.wang@mediatek.com> References: <20220512130715.8165-1-johnson.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree binding of MediaTek CCI on MT8183 and MT8186. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Johnson Wang Signed-off-by: Jia-Wei Chang --- .../bindings/interconnect/mediatek,cci.yaml | 140 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml new file mode 100644 index 000000000000..034c3b38ca3d --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling + +maintainers: + - Jia-Wei Chang + - Johnson Wang + +description: | + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by + MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in + hardware. It can also optimize the voltage to reduce the power consumption. + +properties: + compatible: + enum: + - mediatek,mt8183-cci + - mediatek,mt8186-cci + + clocks: + items: + - description: + The multiplexer for clock input of the bus. + - description: + A parent of "cpu" clock which is used as an intermediate clock source + when the original CPU is under transition and not stable yet. + + clock-names: + items: + - const: cci + - const: intermediate + + operating-points-v2: true + opp-table: true + + proc-supply: + description: + Phandle of the regulator for CCI that provides the supply voltage. + + sram-supply: + description: + Phandle of the regulator for sram of CCI that provides the supply + voltage. When it is present, the implementation needs to do + "voltage tracking" to step by step scale up/down Vproc and Vsram to fit + SoC specific needs. When absent, the voltage scaling flow is handled by + hardware, hence no software "voltage tracking" is needed. + +required: + - compatible + - clocks + - clock-names + - operating-points-v2 + - proc-supply + +additionalProperties: false + +examples: + - | + #include + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + proc-supply = <&mt6358_vproc12_reg>; + }; + + cci_opp: opp-table-cci { + compatible = "operating-points-v2"; + opp-shared; + opp2_00: opp-273000000 { + opp-hz = /bits/ 64 <273000000>; + opp-microvolt = <650000>; + }; + opp2_01: opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + opp-microvolt = <687500>; + }; + opp2_02: opp-403000000 { + opp-hz = /bits/ 64 <403000000>; + opp-microvolt = <718750>; + }; + opp2_03: opp-463000000 { + opp-hz = /bits/ 64 <463000000>; + opp-microvolt = <756250>; + }; + opp2_04: opp-546000000 { + opp-hz = /bits/ 64 <546000000>; + opp-microvolt = <800000>; + }; + opp2_05: opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <818750>; + }; + opp2_06: opp-689000000 { + opp-hz = /bits/ 64 <689000000>; + opp-microvolt = <850000>; + }; + opp2_07: opp-767000000 { + opp-hz = /bits/ 64 <767000000>; + opp-microvolt = <868750>; + }; + opp2_08: opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + opp-microvolt = <893750>; + }; + opp2_09: opp-871000000 { + opp-hz = /bits/ 64 <871000000>; + opp-microvolt = <906250>; + }; + opp2_10: opp-923000000 { + opp-hz = /bits/ 64 <923000000>; + opp-microvolt = <931250>; + }; + opp2_11: opp-962000000 { + opp-hz = /bits/ 64 <962000000>; + opp-microvolt = <943750>; + }; + opp2_12: opp-1027000000 { + opp-hz = /bits/ 64 <1027000000>; + opp-microvolt = <975000>; + }; + opp2_13: opp-1092000000 { + opp-hz = /bits/ 64 <1092000000>; + opp-microvolt = <1000000>; + }; + opp2_14: opp-1144000000 { + opp-hz = /bits/ 64 <1144000000>; + opp-microvolt = <1025000>; + }; + opp2_15: opp-1196000000 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1050000>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index e8c52d0192a6..69f03077f77c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5698,6 +5698,7 @@ L: linux-pm@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git F: Documentation/devicetree/bindings/devfreq/ +F: Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml F: drivers/devfreq/ F: include/linux/devfreq.h F: include/trace/events/devfreq.h -- 2.18.0