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From:   Atish Kumar Patra <atishp@rivosinc.com>
Date:   Thu, 12 May 2022 10:21:56 -0700
Message-ID: <CAHBxVyF5T7r26nAp1Hep+DRkZErr2PH43k=HwLi6iuqMXWju6Q@mail.gmail.com>
Subject: Re: [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32
To:     Anup Patel <anup@brainfault.org>
Cc:     =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Atish Patra <atishp@atishpatra.org>,
        Damien Le Moal <damien.lemoal@wdc.com>,
        DTML <devicetree@vger.kernel.org>,
        Jisheng Zhang <jszhang@kernel.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Rob Herring <robh+dt@kernel.org>
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On Thu, May 12, 2022 at 8:36 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Thu, May 12, 2022 at 6:12 PM Heiko St=C3=BCbner <heiko@sntech.de> wrot=
e:
> >
> > Am Donnerstag, 12. Mai 2022, 06:44:12 CEST schrieb Anup Patel:
> > > On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp@rivosinc.com> wro=
te:
> > > >
> > > > Pass the upper half of the initial value of the counter correctly
> > > > for RV32.
> > > >
> > > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
> > > >
> > > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > > > ---
> > > >  drivers/perf/riscv_pmu_sbi.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_=
sbi.c
> > > > index a1317a483512..24cea59612be 100644
> > > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > > @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(=
struct riscv_pmu *pmu,
> > > >                         max_period =3D riscv_pmu_ctr_get_width_mask=
(event);
> > > >                         init_val =3D local64_read(&hwc->prev_count)=
 & max_period;
> > > >                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_=
START, idx, 1,
> > > > -                                 flag, init_val, 0, 0);
> > > > +                                 flag, init_val, init_val >> 32, 0=
);
> > >
> > > This should be under "#if __riscv_xlen =3D=3D 32".
> >
> > What's the difference between using CONFIG_32BIT
> > and checking the __riscv_xlen flag value?
>
> It's one and the same.
>
> >
> > CONFIG_32BIT seems to be a bit the more kernel'ish
> > way to do this, but it looks like most SBI parts check the
> > __riscv_xlen instead.
>

Not only SBI parts, there are more users of __riscv_xlen compared
CONFIG_32BIT in arch/riscv.

> I agree with you. We should prefer "#ifdef CONFIG_32BIT"
> in this case to match the kernel coding style.
>

Sure. I will change it to CONFIG_32BIT.


> Currently, OpenSBI does not have CONFIG_xyz defines so
> over there we use "#if __riscv_xlen =3D=3D 32".
>
> Regards,
> Anup
>
> >
> >
> > In any case, looking at the opensbi-side of the call,
> > this fix is abviously correct, so
> >
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> >
> >
> >