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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id w18-20020a5d6812000000b0020ae970a187si3265948wru.852.2022.05.13.17.35.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 17:35:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; dkim=pass (test mode) header.i=@ideasonboard.com header.s=mail header.b=i1nSdsuq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B204B33502D; Fri, 13 May 2022 16:26:19 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232890AbiEMNuJ (ORCPT + 99 others); Fri, 13 May 2022 09:50:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381766AbiEMNkA (ORCPT ); Fri, 13 May 2022 09:40:00 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37B3A1208B for ; Fri, 13 May 2022 06:39:46 -0700 (PDT) Received: from pendragon.ideasonboard.com (85-76-5-213-nat.elisa-mobile.fi [85.76.5.213]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id C78C959D; Fri, 13 May 2022 15:39:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1652449184; bh=8/jJDujU6QyrSi/47Vo1bf+z4+ljqIkNHAMhhxf4vkY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=i1nSdsuqrEcfUCKfR5DGq4mA9vssQVDeApG7aBRalDAmZPZU1YgztKy/6mmHPnhdi 56KF0ozHPcm8Iy+dDcxFh9LnFZe9bIX08TivUaD6hS18hYnlQ6YqwrQi7wqEwhQgSc WJmKpJs5ivJMWhYwmnJ3/OTzIkiNMwkXtIbrBPvA= Date: Fri, 13 May 2022 16:39:25 +0300 From: Laurent Pinchart To: Venkateshwar Rao Gannavarapu Cc: dri-devel@lists.freedesktop.org, airlied@linux.ie, daniel@ffwll.ch, linux-kernel@vger.kernel.org, vgannava@xilinx.com Subject: Re: [LINUX PATCH 1/2] dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation Message-ID: References: <1652363593-45799-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> <1652363593-45799-2-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1652363593-45799-2-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi GVRao, Thank you for the patch. On Thu, May 12, 2022 at 07:23:12PM +0530, Venkateshwar Rao Gannavarapu wrote: > This patch adds dt binding for Xilinx DSI TX subsystem. > > The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem > implements the Mobile Industry Processor Interface (MIPI) based display > interface. It supports the interface with the programmable logic (FPGA). > > Signed-off-by: Venkateshwar Rao Gannavarapu > --- > .../bindings/display/xlnx/xlnx,dsi-tx.yaml | 105 +++++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml > > diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml > new file mode 100644 > index 0000000..8e23cf5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi-tx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx DSI Transmitter subsystem > + > +maintainers: > + - Venkateshwar Rao Gannavarapu > + > +description: | > + The Xilinx DSI Transmitter Subsystem implements the Mobile Industry > + Processor Interface based display interface. It supports the interface > + with the programmable logic (FPGA). > + > + For more details refer to PG238 Xilinx MIPI DSI-V2.0 Tx Subsystem. > + > +properties: > + compatible: > + const: xlnx,dsi-tx-v2.0 > + > + reg: > + maxItems: 1 > + > + clocks: > + description: List of clock specifiers You can drop the description, clocks is always a list of clock specifiers. > + items: > + - description: AXI Lite CPU clock > + - description: D-phy clock s/D-phy/D-PHY/ > + > + clock-names: > + items: > + - const: s_axis_aclk > + - const: dphy_clk_200M > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + description: > + Input port node to receive pixel data from the > + display controller. Exactly one endpoint must be > + specified. > + properties: > + endpoint: > + $ref: /schemas/graph.yaml#/properties/endpoint > + description: sub-node describing the input from CRTC "CRTC" is a DRM term, and DT bindings should document the hardware, not the driver. I'd drop the endpoint description as I don't think it brings much, and use /schemas/graph.yaml#/properties/port instead of port-base. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + DSI output port node to the panel or the next bridge > + in the chain Same ere about "bridge". Maybe just description: Output port node to DSI device. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + dsi_tx@80020000 { > + compatible = "xlnx,dsi-tx-v2.0"; > + reg = <0x80020000 0x20000>; > + clock-names = "s_axi_aclk", "dphy_clk_200M"; Wrong clock name. > + clocks = <&misc_clk_0>, <&misc_clk_1>; You need #address-cells = <1> and #size-cells = <0> here to specify an address for the panel. This should have been caught by the schema validation. Please see Documentation/devicetree/bindings/writing-schema.rst for instructions on how to validate bindings. > + > + panel@0 { This will also fail to validate. You need to reference dsi-controller.yaml. You can check the other bindings for DSI controller for examples. > + compatible = "auo,b101uan01"; > + reg = <0>; > + port { > + panel_in: endpoint { > + remote-endpoint = <&mipi_dsi_out>; > + }; > + }; > + }; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + #size-cells = <0>; > + #address-cells = <1>; > + reg = <0>; > + mipi_dsi_in: endpoint@0 { > + reg = <0>; With a single endpoint you can drop the reg as well as the @0, and the size and address cells in the parent. > + remote-endpoint = <&pl_disp_crtc>; > + }; > + }; > + port@1 { > + reg = <1>; > + mipi_dsi_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > + }; > + }; -- Regards, Laurent Pinchart