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Date:   Thu, 12 May 2022 22:23:09 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
Cc:     Parshuram Raju Thombare <pthombar@cadence.com>,
        tjoseph@cadence.com, bhelgaas@google.com, robh@kernel.org,
        kishon@ti.com, kw@linux.com, mparab@cadence.com,
        linux-pci@vger.kernel.org, linux-omap@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] PCI: cadence: Clear FLR in device capabilities
 register
Message-ID: <Yn16vX1cGMt0CVj6@lpieralisi>
References: <165228494389.11307.11313445181760109588.b4-ty@arm.com>
 <20220512190626.GA862290@bhelgaas>
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On Thu, May 12, 2022 at 02:06:26PM -0500, Bjorn Helgaas wrote:
> On Wed, May 11, 2022 at 05:02:35PM +0100, Lorenzo Pieralisi wrote:
> > On Mon, 15 Nov 2021 23:39:16 -0800, Parshuram Raju Thombare wrote:
> > > From: Parshuram Thombare <pthombar@cadence.com>
> > > 
> > > Clear FLR (Function Level Reset) from device capabilities
> > > registers for all physical functions.
> > > 
> > > During FLR, the Margining Lane Status and Margining Lane Control
> > > registers should not be reset, as per PCIe specification.
> > > However, the controller incorrectly resets these registers upon FLR.
> > > This causes PCISIG compliance FLR test to fail. Hence preventing
> > > all functions from advertising FLR support if flag quirk_disable_flr
> > > is set.
> > > 
> > > [...]
> > 
> > Applied to pci/cadence, thanks!
> > 
> > [1/1] PCI: cadence: Clear FLR in device capabilities register
> >       https://git.kernel.org/lpieralisi/pci/c/d3dbd4d862
> 
> Obviously you've already seen the kbuild report:
>   https://lore.kernel.org/r/202205120700.X76G7aC2-lkp@intel.com
> 
> but it looks like most of this patch got lost somehow :)  Happy to fix
> it up for you if you want!

I have messed up the merge, now rebuilt my pci/cadence branch, it
_should_ be fixed, apologies.

Lorenzo