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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OS0PR01MB5922.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: aacd214f-c183-424c-54a3-08da3716b1af X-MS-Exchange-CrossTenant-originalarrivaltime: 16 May 2022 08:33:03.5743 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: W4zB3AnOnEorFl0Fo13Q+60x8AbnrghMlWRaTugXV99WpLj522cRDUXGUo99YRRp29TnKyBrNvKGUFSHeORbNM0fqHv0wRpxYt4ribb03yc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSAPR01MB4001 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, .org>; Phil Edworthy > > Subject: Re: [PATCH v3 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ > domain to handle GPIO interrupt >=20 > On Mon, 16 May 2022 08:20:47 +0100, > Biju Das wrote: > > > > > > > > > > I believe from interrupt statistics point of view, cat > > > > /proc/interrupts should report actual gpioint number (0->122) > > > > corresponding to pin index for SW1, SW2 and SW3 ?? > > > > > > No. There is no need for such userspace-visible behaviour. Userspace > > > has no business tracking those. The required information is in > > > debugfs, and that more than enough. > > > > Ok, So far I used cat /proc/interrupts for debugging, since I don't > > need to enable DEBUG config for Enabling Debugfs for irq. This Debugfs > > irq is new info to me. > > > > Our hardware manual has below info for usb-phy irq > > 2H0_OBINT 126(InterruptID) SPI 94 IRQ 94 Level > > > > cat /proc/interrupts matches with GICV3 Interrupt ID/ type in the HW > manual > > 113: 0 0 GICv3 126 Level 11c50200.usb-phy > > > > Debugfs is also showing similar info like hwirq and interrupt type. > > But I don't know which field corresponds to number of interrupts? > > > > root@smarc-rzg2l:~# cat /sys/kernel/debug/irq/irqs/113 > > handler: handle_fasteoi_irq > > device: (null) > > status: 0x00000104 > > istate: 0x00000000 > > ddepth: 0 > > wdepth: 0 > > dstate: 0x13402204 > > IRQ_TYPE_LEVEL_HIGH > > IRQD_LEVEL > > IRQD_ACTIVATED > > IRQD_IRQ_STARTED > > IRQD_SINGLE_TARGET > > IRQD_DEFAULT_TRIGGER_SET > > IRQD_HANDLE_ENFORCE_IRQCTX > > node: 0 > > affinity: 0-1 > > effectiv: 0 > > domain: :soc:interrupt-controller@11900000-1 > > hwirq: 0x7e >=20 > 0x7e =3D 126 =3D 94 - 32 -> SPI94. >=20 > What else do you need? OK, similar to GIC, I thought for gpio interrupts, The hwirq should match with gpiointN mentioned in hwmanual. That is all. Any way it is minor thing, it may be not at all needed. Please ignore this. Eg:-for gpioint0, it should be root@smarc-rzg2l:~# cat /proc/interrupts | grep SW 82: 0 0 11030000.pinctrl 0 Edge XXX Not like root@smarc-rzg2l:~# cat /proc/interrupts | grep SW 82: 0 0 11030000.pinctrl 120 Edge XXX Cheers, Biju >=20 > > chip: GICv3 > > flags: 0x15 > > IRQCHIP_SET_TYPE_MASKED > > IRQCHIP_MASK_ON_SUSPEND > > IRQCHIP_SKIP_SET_WAKE > > > > Now coming to current case, > > > > Currently GPIO INT 0-122(123 interrupts) corresponding to > > 120-511(291 interrupts) with same invalid lines. > > > > From a debugging point, If user has put same irq name for gpioints(cat > > /proc/interrupts case), then how do we distinguish these interrupts?? > > (using hwirq??) >=20 > Yes. >=20 > > > > For using Debugfs, Do we need to first execute cat /proc/interrupts to > > get virq and from there we need to use virq to get statistics, right? >=20 > It depends what you want to do. /sys/kernel/debug/irq/irqs/ has the exact > same information. The only thing /proc/interrupts has that debugfs doesn'= t > is the per-CPU accounting of delivered interrupts.