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 <20220516152651.GA18461@wintermute.localdomain>
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From:   Peter Geis <pgwipeout@gmail.com>
Date:   Mon, 16 May 2022 17:51:59 -0400
Message-ID: <CAMdYzYp9Yn7VGS3phj+QOP=Bh8+OH3i5oP81Ur_R_egXWYcyig@mail.gmail.com>
Subject: Re: [PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on
 Quartz64 Model A
To:     Chris Morgan <macroalpha82@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Heiko Stuebner <heiko@sntech.de>, linux-clk@vger.kernel.org,
        devicetree <devicetree@vger.kernel.org>,
        arm-mail-list <linux-arm-kernel@lists.infradead.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Mon, May 16, 2022 at 11:26 AM Chris Morgan <macroalpha82@gmail.com> wrote:
>
> On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote:
> > Add the sfc controller binding for the Quartz64 Model A. This is not
> > populated by default, so leave it disabled.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > index 71df64655de5..6ec349e7e521 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > @@ -603,6 +603,22 @@ &sdmmc1 {
> >       status = "okay";
> >  };
> >
> > +&sfc {
> > +     pinctrl-0 = <&fspi_pins>;
> > +     pinctrl-names = "default";
> > +     #address-cells = <1>;
> > +     #size-cells = <0>;
> > +     status = "disabled";
> > +
> > +     flash@0 {
> > +             compatible = "jedec,spi-nor";
> > +             reg = <0>;
> > +             spi-max-frequency = <24000000>;
> > +             spi-rx-bus-width = <4>;
> > +             spi-tx-bus-width = <1>;
>
> This isn't really a concern, just a comment. Did you test this with the
> spi-tx-bus-width of 4 by chance? While I did have to use 1 for my
> implementation (the Odroid Go Advance) the Rockchip engineer I worked
> with couldn't replicate the issue on his end and we ended up chalking
> my issues up to an implementation specific problem. I'm only commenting
> here because I don't want you to think that for this device the tx
> always has to be 1, of course if your implementation does have issues
> with a tx of 2 or 4 that's different...

Yes, and it was a data disaster. Looking into it I found all of the
flash chips that I could find only support 4x RX 1x TX. Some didn't
handle 4x RX terribly well either.

>
> Thank you.
>
> > +     };
> > +};
> > +
> >  /* spdif is exposed on con40 pin 18 */
> >  &spdif {
> >       status = "okay";
> > --
> > 2.25.1
> >