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Date:   Mon, 16 May 2022 13:49:59 -0500
From:   Rob Herring <robh@kernel.org>
To:     Alex Helms <alexander.helms.jy@renesas.com>
Cc:     sboyd@kernel.org, linux-clk@vger.kernel.org,
        mturquette@baylibre.com, linux-kernel@vger.kernel.org,
        michal.simek@xilinx.com, devicetree@vger.kernel.org,
        robh+dt@kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: Renesas versaclock7 device tree bindings
Message-ID: <20220516184959.GA3069296-robh@kernel.org>
References: <20220503194201.25714-1-alexander.helms.jy@renesas.com>
 <20220503194201.25714-2-alexander.helms.jy@renesas.com>
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In-Reply-To: <20220503194201.25714-2-alexander.helms.jy@renesas.com>
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On Tue, 03 May 2022 12:42:00 -0700, Alex Helms wrote:
> Renesas Versaclock7 is a family of configurable clock generator ICs
> with fractional and integer dividers. This driver has basic support
> for the RC21008A device, a clock synthesizer with a crystal input and
> 8 outputs. The supports changing the FOD and IOD rates, and each
> output can be gated.
> 
> Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com>
> ---
>  .../bindings/clock/renesas,versaclock7.yaml   | 64 +++++++++++++++++++
>  MAINTAINERS                                   |  5 ++
>  2 files changed, 69 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>