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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id v196-20020acaaccd000000b00325cda1ff8fsm318670oie.14.2022.05.17.17.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 17:25:30 -0700 (PDT) Received: (nullmailer pid 1933964 invoked by uid 1000); Wed, 18 May 2022 00:25:29 -0000 Date: Tue, 17 May 2022 19:25:29 -0500 From: Rob Herring To: Heiko Stuebner Cc: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, krzk+dt@kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size Message-ID: <20220518002529.GA1928329-robh@kernel.org> References: <20220511214132.2281431-1-heiko@sntech.de> <20220511214132.2281431-2-heiko@sntech.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220511214132.2281431-2-heiko@sntech.de> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,MAILING_LIST_MULTI, RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote: > The Zicbom operates on a block-size defined for the cpu-core, > which does not necessarily match other cache-sizes used. > > So add the necessary property for the system to know the core's > block-size. > > Signed-off-by: Heiko Stuebner > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d632ac76532e..b179bfd155a3 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -63,6 +63,13 @@ properties: > - riscv,sv48 > - riscv,none > > + riscv,cbom-block-size: > + $ref: /schemas/types.yaml#/definitions/uint32 Any value 0-2^32 is valid? > + description: > + Blocksize in bytes for the Zicbom cache operations. The block > + size is a property of the core itself and does not necessarily > + match other software defined cache sizes. What about hardware defined cache sizes? I'm scratching my head as to what a 'software defined cache size' is. > + > riscv,isa: > description: > Identifies the specific RISC-V instruction set architecture > -- > 2.35.1 > >