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From:   Anup Patel <anup@brainfault.org>
Date:   Wed, 18 May 2022 14:40:17 +0530
Message-ID: <CAAhSdy1sG8uzg0W2Ufi=EYFB58+JZobUa9D+rcHeb4upJoMzng@mail.gmail.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size
To:     =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>
Cc:     Rob Herring <robh@kernel.org>,
        Philipp Tomsich <philipp.tomsich@vrull.eu>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        Wei Fu <wefu@redhat.com>, Guo Ren <guoren@kernel.org>,
        Atish Patra <atishp@atishpatra.org>,
        Nick Kossifidis <mick@ics.forth.gr>,
        Samuel Holland <samuel@sholland.org>,
        Christoph Muellner <cmuellner@linux.com>, krzk+dt@kernel.org,
        DTML <devicetree@vger.kernel.org>
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On Wed, May 18, 2022 at 2:33 PM Heiko St=C3=BCbner <heiko@sntech.de> wrote:
>
> Am Mittwoch, 18. Mai 2022, 10:22:17 CEST schrieb Philipp Tomsich:
> > +David Kruckemyer (who is chairing the CMO task-group within RVI).
> >
> > On Wed, 18 May 2022 at 02:25, Rob Herring <robh@kernel.org> wrote:
> > >
> > > On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote:
> > > > The Zicbom operates on a block-size defined for the cpu-core,
> > > > which does not necessarily match other cache-sizes used.
> > > >
> > > > So add the necessary property for the system to know the core's
> > > > block-size.
> > > >
> > > > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > > > ---
> > > >  Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
> > > >  1 file changed, 7 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Do=
cumentation/devicetree/bindings/riscv/cpus.yaml
> > > > index d632ac76532e..b179bfd155a3 100644
> > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > > @@ -63,6 +63,13 @@ properties:
> > > >        - riscv,sv48
> > > >        - riscv,none
> > > >
> > > > +  riscv,cbom-block-size:
> > > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > >
> > > Any value 0-2^32 is valid?
> > >
> > > > +    description:
> > > > +      Blocksize in bytes for the Zicbom cache operations. The bloc=
k
> > > > +      size is a property of the core itself and does not necessari=
ly
> > > > +      match other software defined cache sizes.
> > >
> > > What about hardware defined cache sizes? I'm scratching my head as to
> > > what a 'software defined cache size' is.
>
> I agree that this should be worded better. The intent was to tell that th=
is
> is different from say the l1-cache-block-size.
>
> I.e. these values can be the same but don't need to be. But I guess I got
> too much lead on by a kernel implementation detail (L1_CACHE_BYTES consta=
nt)

Better to just call it as "the cache block-size expected by Zicbom cache
operations" without getting details of relation with L1 cache block size.

Regards,
Anup

>
>
> > This seems to be a misnomer, as the specification doesn't use the term
> > and rather talks about the "size of a cache block for [operation
> > name]".
> >
> > There are currently two such 'operation sizes' discoverable by software=
:
> > - size of the cache block for management and prefetch instructions
> > - size of the cache block for zero instructions
> >
> > For whatever it's worth, cache operations in RISC-V attempt to
> > disassociate the underlying hardware cache geometry from software.
> > See https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmob=
ase-v1.0.1.pdf
> > for the CMO specification, and the discoverable parameters are listed
> > in section 2.7.
> >
> > Philipp.
> >
> > > > +
> > > >    riscv,isa:
> > > >      description:
> > > >        Identifies the specific RISC-V instruction set architecture
> > > > --
> > > > 2.35.1
> > > >
> > > >
> >
>
>
>
>