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From:   "VURDIGERENATARAJ, CHANDAN" <CHANDAN.VURDIGERENATARAJ@amd.com>
To:     Sasha Levin <sashal@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "stable@vger.kernel.org" <stable@vger.kernel.org>
CC:     "Yang, Eric" <Eric.Yang2@amd.com>,
        "haonan.wang2@amd.com" <haonan.wang2@amd.com>,
        "Li, Sun peng (Leo)" <Sunpeng.Li@amd.com>,
        "Pan, Xinhui" <Xinhui.Pan@amd.com>,
        "Siqueira, Rodrigo" <Rodrigo.Siqueira@amd.com>,
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        "Deucher, Alexander" <Alexander.Deucher@amd.com>,
        "mikita.lipski@amd.com" <mikita.lipski@amd.com>,
        "Wentland, Harry" <Harry.Wentland@amd.com>,
        "Kazlauskas, Nicholas" <Nicholas.Kazlauskas@amd.com>,
        "Kotarac, Pavle" <Pavle.Kotarac@amd.com>
Subject: RE: [PATCH AUTOSEL 5.17 13/23] drm/amd/display: undo clearing of z10
 related function pointers
Thread-Topic: [PATCH AUTOSEL 5.17 13/23] drm/amd/display: undo clearing of z10
 related function pointers
Thread-Index: AQHYarKiOZP/iIcp70e9k8jQNn0/Va0kkcYw
Date:   Wed, 18 May 2022 12:36:40 +0000
Message-ID: <MW4PR12MB5668AA4277ABA5A76CAABB1F96D19@MW4PR12MB5668.namprd12.prod.outlook.com>
References: <20220518122641.342120-1-sashal@kernel.org>
 <20220518122641.342120-13-sashal@kernel.org>
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Hi,

Is S0i3 verified for DCN 3.1.6 with this?

BR,
Chandan V N

>From: Eric Yang <Eric.Yang2@amd.com>
>
>[ Upstream commit 9b9bd3f640640f94272a461b2dfe558f91b322c5 ]
>
> [Why]
>Z10 and S0i3 have some shared path. Previous code clean up , incorrectly r=
emoved these pointers, which breaks s0i3 restore
>
> [How]
>Do not clear the function pointers based on Z10 disable.
>
>Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
>Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
>Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>Signed-off-by: Sasha Levin <sashal@kernel.org>
>---
> drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 5 -----
> 1 file changed, 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/g=
pu/drm/amd/display/dc/dcn31/dcn31_init.c
>index d7559e5a99ce..e708f07fe75a 100644
>--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
>+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
>@@ -153,9 +153,4 @@ void dcn31_hw_sequencer_construct(struct dc *dc)
> 		dc->hwss.init_hw =3D dcn20_fpga_init_hw;
> 		dc->hwseq->funcs.init_pipes =3D NULL;
> 	}
>-	if (dc->debug.disable_z10) {
>-		/*hw not support z10 or sw disable it*/
>-		dc->hwss.z10_restore =3D NULL;
>-		dc->hwss.z10_save_init =3D NULL;
>-	}
> }
>--
>2.35.1
>