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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u18-20020a056a00125200b004fa3a8e0087si7734446pfi.318.2022.05.19.09.15.13; Thu, 19 May 2022 09:15:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qAA8lOXG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238692AbiESNV1 (ORCPT + 99 others); Thu, 19 May 2022 09:21:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238682AbiESNVY (ORCPT ); Thu, 19 May 2022 09:21:24 -0400 Received: from mail-yb1-xb36.google.com (mail-yb1-xb36.google.com [IPv6:2607:f8b0:4864:20::b36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F329E13D3A for ; Thu, 19 May 2022 06:21:22 -0700 (PDT) Received: by mail-yb1-xb36.google.com with SMTP id i187so6778719ybg.6 for ; Thu, 19 May 2022 06:21:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/8rkuhaZCQOmIIWlvL2cVDQe2QMeTYPgrGWngEZIrx4=; b=qAA8lOXG8uIzKLnoeK5xsx2x0vRWX6tIuU9hSyCXncTSHBvHstrpTc1JZ2HDD3F2i3 ZiJShiWWKUvTsCocOYW3LlqNcwSZxAw1B17JguGYGXm9o4c/Ek35ZgLsaqrPYMeRxM3h dtkxIKXN0cMeYzdq/p9LKfP1XzkcvsZkNkh5eLdQdw15AK5kP9rFQL/BOHi36WsAHR1I Iny/GWuPfSty3YalC4ZbKxm6kNV/C24UCgpxKW011EinRM7XCCpE0vvdoumFNoGNp39K MMqaKtM4GWk9RaCv87OsZr0ywEpbFiQ2OEArEnn88yAjH2sJtRabYx/32nWpvP/haUdB 3vDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/8rkuhaZCQOmIIWlvL2cVDQe2QMeTYPgrGWngEZIrx4=; b=Z3hyPxq8bMNizI7UH7cWDQo79YdffLA9e+8rsDAzyDpVFl0fQjfvtB8RZ0gQPjLGtN Awdt5VYBAmkvJr79pWbPzRlgbSbigSgMbfLoHxfoI/sdy+amfcO2IDIj50cKb3NnFk3P wO2k6VZ0Dcp4WB0NVikWcsLiase1RWQ2bg4OPhuEZ1S0maKAobm0m3o+Uyvp1W6jjZV7 AAFtx2Y/2QsHIofUTKRIKP3aGso0Ra0JvcbBnZlM7soVXkXZ0mPnPmQmv0J+tzmhxGR2 emH5rg6jkAF6XnfdyMuWMSKZqXdzrk94eIAeZqaSh9S8Si+jaPZtbMDMhxKcW1bLqAo6 N/LA== X-Gm-Message-State: AOAM531b7nNnuNkglPJIf4fU6/hi1c6zQWj/Q7T3JKFznOvw97jOUlV9 GN2cYjnqF+TrSpgRFlQHU7I5o4vjwD/D2wmDhgLB4A== X-Received: by 2002:a05:6902:526:b0:64d:b6ab:f91d with SMTP id y6-20020a056902052600b0064db6abf91dmr4494072ybs.295.1652966482209; Thu, 19 May 2022 06:21:22 -0700 (PDT) MIME-Version: 1.0 References: <20220511183210.5248-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220511183210.5248-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Linus Walleij Date: Thu, 19 May 2022 15:21:10 +0200 Message-ID: Subject: Re: [PATCH v3 4/5] gpio: gpiolib: Add ngirq member to struct gpio_irq_chip To: "Lad, Prabhakar" Cc: Lad Prabhakar , Geert Uytterhoeven , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Bartosz Golaszewski , Philipp Zabel , "open list:GPIO SUBSYSTEM" , LKML , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Phil Edworthy , Biju Das Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 18, 2022 at 8:36 PM Lad, Prabhakar wrote: > > As Geert says, I think you can just use .valid_mask for this, > > what do you say? > > > I don't think Geert is suggesting that. The .valid_mask option is one > time setting but what I need is something dynamic i.e. out of 392 GPIO > pins any 32 can be used as an interrupt pin. So why can't this just be determined from the compatible? This does not sound like a configuration option at all but something related to the IP block per se, and then you know that if it has a certain compatible then it has this property. Yours, Linus Walleij