Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760131AbXEOG2G (ORCPT ); Tue, 15 May 2007 02:28:06 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1760668AbXEOG1z (ORCPT ); Tue, 15 May 2007 02:27:55 -0400 Received: from imx12.toshiba.co.jp ([61.202.160.132]:53440 "EHLO imx12.toshiba.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759441AbXEOG1y (ORCPT ); Tue, 15 May 2007 02:27:54 -0400 Date: Tue, 15 May 2007 15:27:26 +0900 Message-ID: From: Tsutomu OWA To: Arnd Bergmann Cc: linuxppc-dev@ozlabs.org, Thomas Gleixner , mingo@elte.hu, linux-kernel@vger.kernel.org Subject: Re: [patch 4/4] powerpc 2.6.21-rt1: reduce scheduling latency by changing tlb flush size In-Reply-To: <200705141640.02561.arnd@arndb.de> References: <1179125506.22481.297.camel@localhost.localdomain> <200705141640.02561.arnd@arndb.de> User-Agent: Wanderlust/2.8.1 (Something) Emacs/20.7 Mule/4.0 (HANANOEN) Organization: Software Engineering Center, TOSHIBA. MIME-Version: 1.0 (generated by SEMI 1.14.4 - "Hosorogi") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1796 Lines: 57 At Mon, 14 May 2007 16:40:02 +0200, Arnd Bergmann wrote: > > +#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT) > > +/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb && RT */ > > +#define PPC64_TLB_BATCH_NR 1 > With this code, you get silent side-effects of enabling PPC_CELLEB > along with another platform. > Maybe instead you should change the hpte_need_flush() to always flush > when running on the celleb platform and PREEMPT_RT is enabled. OK, how about this one? thanks a lot! Since flushing tlb needs expensive hypervisor call(s) on celleb, always flush it on RT to reduce scheduling latency. Signed-off-by: Tsutomu OWA -- owa --- linux-2.6.21-rt1/arch/powerpc/mm/tlb_64.c 2007-05-07 14:08:12.000000000 +0900 +++ rt/arch/powerpc/mm/tlb_64.c 2007-05-15 15:19:34.000000000 +0900 @@ -31,6 +31,7 @@ #include #include #include +#include DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); @@ -180,6 +181,18 @@ void hpte_update(struct mm_struct *mm, u batch->vaddr[i] = (vsid << 28 ) | (addr & 0x0fffffff); batch->pte[i] = __real_pte(__pte(pte), ptep); batch->index = ++i; + +#ifdef CONFIG_PREEMPT_RT + /* + * Since flushing tlb needs expensive hypervisor call(s) on celleb, + * always flush it on RT to reduce scheduling latency. + */ + if (machine_is(celleb)) { + flush_tlb_pending(); + return; + } +#endif /* CONFIG_PREEMPT_RT */ + if (i >= PPC64_TLB_BATCH_NR) flush_tlb_pending(); } - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/