Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <25ebba62-0100-f7af-80fa-556fd6c2e879@amd.com>
Date:   Fri, 20 May 2022 10:50:45 +0530
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101
 Thunderbird/91.4.1
Subject: Re: [PATCH v3 2/5] perf header: Parse non-cpu pmu capabilities
Content-Language: en-US
To:     Ian Rogers <irogers@google.com>
Cc:     acme@kernel.org, peterz@infradead.org, rrichter@amd.com,
        mingo@redhat.com, mark.rutland@arm.com, jolsa@kernel.org,
        namhyung@kernel.org, tglx@linutronix.de, bp@alien8.de,
        james.clark@arm.com, leo.yan@linaro.org, kan.liang@linux.intel.com,
        ak@linux.intel.com, eranian@google.com, like.xu.linux@gmail.com,
        x86@kernel.org, linux-perf-users@vger.kernel.org,
        linux-kernel@vger.kernel.org, sandipan.das@amd.com,
        ananth.narayan@amd.com, kim.phillips@amd.com,
        santosh.shukla@amd.com, Ravi Bangoria <ravi.bangoria@amd.com>
References: <20220519054355.477-1-ravi.bangoria@amd.com>
 <20220519054355.477-3-ravi.bangoria@amd.com>
 <CAP-5=fXiZj+EBqmg89faK0pZD-Af3V1fHWMOkds1oKoaz+ucFA@mail.gmail.com>
 <e578d274-946f-2c73-026d-9b172ce32f19@amd.com>
 <CAP-5=fXJQcVEUEz3taSXsm0Kd0Fs3Vc4+++vz1fVEHLjB3nMPw@mail.gmail.com>
From:   Ravi Bangoria <ravi.bangoria@amd.com>
In-Reply-To: <CAP-5=fXJQcVEUEz3taSXsm0Kd0Fs3Vc4+++vz1fVEHLjB3nMPw@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?RDZNODMyNmlubm92emw2cUsyT2dWWCtkcytpVVV6Y1lyMktpV25KMUpXSzVx?=
 =?utf-8?B?SitEWXY4RFQ3WFBDUWJnd3ZtT2VUa1pGMzJwWDREdXA1MGhtSHRaRGVJVTJG?=
 =?utf-8?B?bFBvL0NmZWZ4SkVOQUc2cVRmcGJhTm9rT1FBTWFzM0gweEFFZHNDLzhiekQ5?=
 =?utf-8?B?ZFMxU284UldYMXZ6WTFDYitGY0hYTTZvZlExbXE3VGgzcHJ4RkpSTktXZVIz?=
 =?utf-8?B?NEJQcWt3ZWQ0c1pjZGljcWZMUFVObUN1NXoySXc4MnErYW14cXZlZlUvQnJF?=
 =?utf-8?B?OFpibElMMFNCVzg1VDEyM0phL0FmeXVXS2Z4VjNMc3piaHdRQlJ5VUUwVHFr?=
 =?utf-8?B?NzVrQThrWjdxd1MycDVuRzEyQk1TWTVpSUt5R0tub2xPaWxWbzdYd1FWbFVW?=
 =?utf-8?B?N2dPSFB5cFF6TVpKQ05FWlo3SHY5RXVSbFpweEV0eCtPVGF1M1VnbUFwa2tC?=
 =?utf-8?B?UFFrWVVzblU5M29vRkJzYVBZZjRoTURvTVp2ZWY3aHVLcVJpYzJVV29QMlp0?=
 =?utf-8?B?ODFnVUFEZlJ0T3pNbnAwbmFyTWsxazRRd2xaSVo2cFNYMlJVSnZqekhqUWZi?=
 =?utf-8?B?ZzQ2cklra0RxQ2F3ZVFUa29wNG1qNmg3dFZXTWFoYWRxZ0RnOEJod3ZqSm1T?=
 =?utf-8?B?RDlNYWtxRmpLVlRsQXRvcG5ZRkJYZDNsQjByOHNKR2NtTkVaVHFGSS9LeEpY?=
 =?utf-8?B?YzA0TGZQR2dVWUw0MmV3ODZ6SFVRRG9VRFloV1FyeC9DZk1KSm0wc1ZVY0hq?=
 =?utf-8?B?OHUvRnByN2xhaU8wcG1aMnAyREU2OERVSmJReXV5ZXNyWTYvalJKQzJGeEpU?=
 =?utf-8?B?MnZFeFVSbVlIY2pHcHRIQlg4cnMzeUVZODI5Z0lBOXUyRWFvWm5veU50aDVV?=
 =?utf-8?B?TUVRWXljRzJDTXBld1FGemtNcW54MjNIaVhiV1lEZWtqL3lMNzZBTHBLMGdV?=
 =?utf-8?B?Zi9vaFNmVUlEUCt3QTVCMWFVYVRacnY0TXdIZ2xDdVVkNzRVamVCQXJMdjVs?=
 =?utf-8?B?WmFZaVBGWFRNdUU2UjMrSjVyNEE3VDNDN3gvc0FFMlBqS2tDYW1IQVZUNDZh?=
 =?utf-8?B?cFlnUEs1QlUrMHB6ak0yeXdrTEpFbkJYUC9tMFNBSHFmRjhCWmtsVGtGU3pE?=
 =?utf-8?B?MVVWU2tTYnBHclJGYXNucFhxTDd5U1BjeWhxbkJGdStrVlZmaUdjcFR0WUhD?=
 =?utf-8?B?Z3p5YTk3R3BUL3ZvWTVSL01taHgxa2FlUE9GaVZRUmJkNnp0b0dpTnQ1S1VL?=
 =?utf-8?B?QlBjZThtT2VhUUpIM1B1M2srbU53UElUVFJKVHlUMFVKaDJkbE5JUzZsVzlt?=
 =?utf-8?B?Y2oyTDY2MVMvWTJXczRJem9MdnZqU0hrOGVDZjQxSk9GQjN4L1hycDhiY25F?=
 =?utf-8?B?eWt0L2N3V3ErWXJxV09BTnRIWWZUVVFqY3ZrSzZUeXN0bGhnRzYzbWhPdkhr?=
 =?utf-8?B?bVk1NUJxSDRvWmR1aDFWOXQzekgxbDN4bW5YM2h5SlBPcXluYW9kelBTQzlY?=
 =?utf-8?B?amFrblNaaDNaVkxMTVRkbG0xYXRVUldCRXFuSS9LcVdYVWZSVnIxMjZCMnhn?=
 =?utf-8?B?VWlKV0hocFdMaEZTZ1VKeGpvZy8yTEViV3dkN3RORmNPRjBFdnlTckJFOGM4?=
 =?utf-8?B?OEFhekRYbUNmU29ZRDE3bmJZRzdsZWxjU3dLZTdpb3RyMU0rZVhRYWRWSzNZ?=
 =?utf-8?B?Wis0RnRaVDJmTDNiS1ZmUkJZU3VOS04wNUkwWGZPTGZVQ0FEZjRnSW9VZy95?=
 =?utf-8?B?Y29jOXVHYlZzelQ2b1hUVW5kNmNzdkxPQk9wbC80YkRVZUh5SER4MlZyOFJP?=
 =?utf-8?B?YWR2WEEzc1ZxLytRQ3lZejQrRThhRXdDMU1LanhlbmxFQzVJbjY3aU1yR216?=
 =?utf-8?B?dDNpNTBQT2FORm9OTFpZek5Ya05kZ3BhVXBLWktveVd1SmdZQTNxRDJXRVhp?=
 =?utf-8?B?VE05eDVPQUM3WStzNFQvdFlaOUkzOGFLNzhmYkwySVJ2bXF3d2dvZ2xDT3A1?=
 =?utf-8?B?dERuNVRjVTF6Wnk0MHI3ZnppWGlMdlBITEExUndYUWtvMXpPMjlWeDY3ZnNO?=
 =?utf-8?B?SXUyMkNwb0M4V05HU1NvVHU1WTJpd2JOcFRnNzRvVTRvbWhxb3RxbWd0VFVG?=
 =?utf-8?B?TWxETkpOeHRmSXNHVnk3UUcyNlpUaThNZzlRWFR5YzRLT0o0aStuZHE1ZkdH?=
 =?utf-8?B?VTZ3QUtpZThjVkEwVG81L3JkZTdRak9pQTBvcFcvbzIyYTdDVEJCa1JUQTVv?=
 =?utf-8?B?akcyYnZFYTNhc2RWK2ZqVWo0bC9wL3RqWm5RV3lmV0hFMUNzaVdhVkFVN2px?=
 =?utf-8?B?bWFYQ3V0bEROak1oOWswd1M5Tlo0R3JCU0l4TTloTGdCcUxCLzRVdz09?=
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 07b538de-0d81-4ed9-394b-08da3a2088e1
X-MS-Exchange-CrossTenant-AuthSource: PH7PR12MB6588.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2022 05:21:04.0702
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: Ql2SFX2fVFBIjdo68L4tQUGD9k+73Yhzf9OMU6YL4wK0y0HHKyyNoFmSvCa+Hjn8De3qMMPlkwUGtwx9sGWynw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3090
X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE
        autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 20-May-22 10:01 AM, Ian Rogers wrote:
> On Thu, May 19, 2022 at 8:49 PM Ravi Bangoria <ravi.bangoria@amd.com> wrote:
>>
>> Hi Ian,
>>
>> On 20-May-22 3:57 AM, Ian Rogers wrote:
>>> On Wed, May 18, 2022 at 10:45 PM Ravi Bangoria <ravi.bangoria@amd.com> wrote:
>>>>
>>>> Pmus advertise their capabilities via sysfs attribute files but
>>>> perf tool currently parses only core(cpu) pmu capabilities. Add
>>>> support for parsing non-cpu pmu capabilities.
>>>>
>>>> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
>>>> ---
>>>>  .../Documentation/perf.data-file-format.txt   |  18 ++
>>>>  tools/perf/util/env.c                         |  48 +++++
>>>>  tools/perf/util/env.h                         |  11 +
>>>>  tools/perf/util/header.c                      | 198 ++++++++++++++++++
>>>>  tools/perf/util/header.h                      |   1 +
>>>>  tools/perf/util/pmu.c                         |  15 +-
>>>>  tools/perf/util/pmu.h                         |   2 +
>>>>  7 files changed, 289 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/tools/perf/Documentation/perf.data-file-format.txt b/tools/perf/Documentation/perf.data-file-format.txt
>>>> index f56d0e0fbff6..7f8341db9134 100644
>>>> --- a/tools/perf/Documentation/perf.data-file-format.txt
>>>> +++ b/tools/perf/Documentation/perf.data-file-format.txt
>>>> @@ -435,6 +435,24 @@ struct {
>>>>         } [nr_pmu];
>>>>  };
>>>>
>>>> +       HEADER_PMU_CAPS = 32,
>>>> +
>>>> +       List of pmu capabilities (except cpu pmu which is already
>>>> +       covered by HEADER_CPU_PMU_CAPS)
>>>
>>> Sorry for the ignorance, is this currently broken for hybrid then?
>>> Will hybrid have a HEADER_CPU_PMU_CAPS? Presumably this varies between
>>> ARM's big.little and Alderlake.
>>
>> It's covered by HEADER_HYBRID_CPU_PMU_CAPS, but that too covers only
>> cpu pmu. I think I should update the above comment to:
>>
>>         List of pmu capabilities (except cpu pmu which is already
>>         covered by HEADER_CPU_PMU_CAPS / HEADER_HYBRID_CPU_PMU_CAPS)
>>
>>>> +
>>>> +struct {
>>>> +       u32 nr_pmus;
>>>> +       struct {
>>>> +               u32 core_type;  /* For hybrid topology */
>>>
>>> Could this be pmu_type as presumably we can have capabilities on any
>>> kind of PMU?
>>
>> Not sure I follow that question but let me just put my thoughts here.
>>
>> {core_type, pmu_name} is the unique key here. Considering a hypothetical
>> scenario: A system has two types of cores P-core and E-core. Certain pmu
>> inside P-core has some capabilities which are missing in the identical
>> pmu belonging to E-core. The header will look something like:
>>
>> struct {
>>         .nr_pmus = 2,
>>         [0] = struct {
>>                 .core_type = 0, /* P-core */
>>                 .pmu_name = xyz_pmu,
>>                 .nr_caps = 2,
>>                 [0] = { .name = cap1, .value = value1 },
>>                 [1] = { .name = cap2, .value = value2 },
>>         },
>>         [1] = struct {
>>                 .core_type = 1; /* E-core */
>>                 .pmu_name = xyz_pmu;
>>                 .nr_caps = 1;
>>                 [0] = { .name = cap1, .value = value1 };
>>         },
>> };
>>
>> Does that answer your question?
>>
>> Thanks for the review,
>> Ravi
> 
> I may be being a little ahead of the current code as I'm wondering
> about heterogeneous systems with many non-CPU PMUs. It seems such a
> scenario just wouldn't touch the core_type field here. Could the p or
> e core-ness of a PMU be implied by the name?

Using just pmu_name to identify the type of core it belongs to; yeah
that might work assuming perf_pmu_register() doesn't allow registering
multiple pmus with the same name. I'll remove 'core_type'.

> Is there something similar to core_type in sysfs

I don't think so. I don't have any Intel ADL or ARM big.LITTLE system
to try. But that's not required now.

Thanks,
Ravi