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Date:   Sat, 21 May 2022 07:53:09 +0200
From:   Wolfram Sang <wsa@kernel.org>
To:     Tyrone Ting <warp5tw@gmail.com>
Cc:     avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com,
        venture@google.com, yuenn@google.com, benjaminfair@google.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        andriy.shevchenko@linux.intel.com, jarkko.nikula@linux.intel.com,
        semen.protsenko@linaro.org, rafal@milecki.pl, sven@svenpeter.dev,
        jsd@semihalf.com, jie.deng@intel.com, lukas.bulwahn@gmail.com,
        arnd@arndb.de, olof@lixom.net, tali.perry@nuvoton.com,
        Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com,
        KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com,
        openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 06/10] i2c: npcm: Correct register access width
Message-ID: <Yoh+RUTtmiQsrCg3@shikoro>
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        Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com,
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References: <20220517101142.28421-1-warp5tw@gmail.com>
 <20220517101142.28421-7-warp5tw@gmail.com>
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On Tue, May 17, 2022 at 06:11:38PM +0800, Tyrone Ting wrote:
> From: Tyrone Ting <kfting@nuvoton.com>
>=20
> The SMBnCTL3 register is 8-bit wide and the 32-bit access was always
> incorrect, but simply didn't cause a visible error on the 32-bit machine.
>=20
> On the 64-bit machine, the kernel message reports that ESR value is
> 0x96000021. Checking Arm Architecture Reference Manual Armv8 suggests that
> it's the alignment fault.
>=20
> SMBnCTL3's address is 0xE.
>=20
> Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller drive=
r")
> Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
> Reviewed-by: Jonathan Neusch=C3=A4fer <j.neuschaefer@gmx.net>

Applied to for-next, thanks!


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