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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB4138.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5df273a3-cfde-4a8b-3396-08da3ae2c983 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 May 2022 04:31:34.3872 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fSeL6RTt5/H+RYnqqcl7TTdJWqRVkEY+JRs2qjG3esO3CQyeBCwBYtuMYVVugTHPR43cnE5Y+/yzFJ4eMFmX9Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4476 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Sean Christopherson > Sent: Saturday, May 21, 2022 12:32 AM > To: Xu, Yanfei > Cc: pbonzini@redhat.com; vkuznets@redhat.com; wanpengli@tencent.com; > jmattson@google.com; joro@8bytes.org; tglx@linutronix.de; > mingo@redhat.com; bp@alien8.de; dave.hansen@linux.intel.com; > x86@kernel.org; kvm@vger.kernel.org; linux-kernel@vger.kernel.org; Wang, > Wei W ; Liang, Kan > Subject: Re: [PATCH] KVM: x86: Fix the intel_pt PMI handling wrongly cons= idered > from guest >=20 > Please don't top-post. Got it, just correctly configured my mailbox with prefix each line of origi= nal message. >=20 > On Fri, May 20, 2022, Xu, Yanfei wrote: > > From: Sean Christopherson On Mon, May 16, 2022, > > Yanfei Xu wrote: > > > diff --git a/arch/x86/include/asm/kvm_host.h > > > b/arch/x86/include/asm/kvm_host.h index 4ff36610af6a..308cf19f123d > > > 100644 > > > --- a/arch/x86/include/asm/kvm_host.h > > > +++ b/arch/x86/include/asm/kvm_host.h > > > @@ -1582,8 +1582,14 @@ static inline int > kvm_arch_flush_remote_tlb(struct kvm *kvm) > > > return -ENOTSUPP; > > > } > > > > > > +enum kvm_intr_type { > > > + /* Values are arbitrary, but must be non-zero. */ > > > + KVM_HANDLING_IRQ =3D 1, > > > + KVM_HANDLING_NMI, > > > +}; > > > + > > > #define kvm_arch_pmi_in_guest(vcpu) \ > > > - ((vcpu) && (vcpu)->arch.handling_intr_from_guest) > > > + ((vcpu) && (vcpu)->arch.handling_intr_from_guest =3D=3D > > > +KVM_HANDLING_NMI) > > > > My understanding is that this isn't correct as a general change, as > > perf events can use regular IRQs in some cases. See commit dd60d217062= f4 > ("KVM: > > x86: Fix perf timer mode IP reporting"). > > > > I assume there's got to be a way to know which mode perf is using, > > e.g. we should be able to make this look something like: > > > > ((vcpu) && (vcpu)->arch.handling_intr_from_guest =3D=3D kvm_pmi_vector= ) >=20 > > Hi Sean, > > You are right, the change of kvm_arch_pmi_in_guest is incorrect, becaus= e it > should cover two cases of PMI. > > For the PMI of intel pt, it certainly is the NMI PMI. So how about fixi= ng it like > below? >=20 > Yep, that works. I did enough spelunking to figure out how we can fix th= e > generic issue, but it's per-event and requires a decent amount of plumbin= g in > perf. Agree, it's per-event for the generic issue... >=20 > perf_guest_handle_intel_pt_intr() doesn't bother with perf_guest_state() = since > it's such a specialized event, so fixing this in vmx_handle_intel_pt_intr= () would > likely be the long-term solution even if/when the generic case is fixed. Will send the v2. Thanks, Yanfei