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References: <20220516165740.6256af51.alex.williamson@redhat.com>
 <20220518115432.76183-1-windy.bi.enflame@gmail.com> <20220520064148.GA20418@wunner.de>
 <CAGdb+H2_pX4TzG=sJ8XE6KiyWW9niJQawCbcDN2byxDfybukiA@mail.gmail.com> <20220521124910.GA13556@wunner.de>
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From:   Sheng Bi <windy.bi.enflame@gmail.com>
Date:   Sun, 22 May 2022 01:37:50 +0800
Message-ID: <CAGdb+H19bfbXM1cPJvhh6gixJbF7Sk=v53d9VpvWY8HEs0mSKg@mail.gmail.com>
Subject: Re: [PATCH v2] PCI: Fix no-op wait after secondary bus reset
To:     Lukas Wunner <lukas@wunner.de>
Cc:     Bjorn Helgaas <helgaas@kernel.org>,
        Alex Williamson <alex.williamson@redhat.com>,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
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On Sat, May 21, 2022 at 8:49 PM Lukas Wunner <lukas@wunner.de> wrote:
>
> On Sat, May 21, 2022 at 04:36:10PM +0800, Sheng Bi wrote:
> > If so, I also want to align the polling things mentioned in the
> > question from Alex, since pci_dev_wait() is also used for reset
> > functions other than SBR. To Bjorn, Alex, Lucas, how do you think if
> > we need to change the polling in pci_dev_wait() to 20ms intervals, or
> > keep binary exponential back-off with probable unexpected extra
> > timeout delay.
>
> The exponential backoff should probably be capped at some point
> to avoid excessive wait delays.  I guess the rationale for
> exponential backoff is to not poll too frequently.
> Capping at 20 msec or 100 msec may be reasonable, i.e.:
>
> -               delay *= 2;
> +               delay = min(delay * 2, 100);
>
> Thanks,
>
> Lukas

Capping at 20 or 100 msec seems reasonable to me. Btw, since 20 msec
is not a long time in these scenarios, how about changing to a fixed
20 msec interval? Thanks,

windy