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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id r26-20020a2e995a000000b0024f3d1daea0sm724179ljj.40.2022.05.21.07.25.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 May 2022 07:25:08 -0700 (PDT) Message-ID: <7fd80a4b-5e60-0117-b790-359f6d94aeef@linaro.org> Date: Sat, 21 May 2022 16:25:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH] dt-bindings: mips: Convert plain text file to ReST Content-Language: en-US To: Soumya Negi , Shuah Khan , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski Cc: linux-kernel-mentees@lists.linuxfoundation.org, linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220521015613.6197-1-soumya.negi97@gmail.com> From: Krzysztof Kozlowski In-Reply-To: <20220521015613.6197-1-soumya.negi97@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,RDNS_NONE,SPF_HELO_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/05/2022 03:56, Soumya Negi wrote: > Converts .txt documentation file to ReST format(.rst). > > Signed-off-by: Soumya Negi > --- > .../devicetree/bindings/mips/cpu_irq.rst | 56 +++++++++++++++++++ > 1 file changed, 56 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.rst > > diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.rst b/Documentation/devicetree/bindings/mips/cpu_irq.rst > new file mode 100644 > index 000000000000..601cc12caa2a > --- /dev/null > +++ b/Documentation/devicetree/bindings/mips/cpu_irq.rst > @@ -0,0 +1,56 @@ > +============================= > +MIPS CPU interrupt controller > +============================= > + > +On MIPS the ``mips_cpu_irq_of_init()`` helper can be used to initialize the 8 CPU > +IRQs from a devicetree file and create a ``irq_domain`` for IRQ controller. Bindings is not a place for code. No. > + > +With the ``irq_domain`` in place we can describe how the 8 IRQs are wired to the > +platforms internal interrupt controller cascade. > + > +Below is an example of a platform describing the cascade inside the devicetree > +and the code used to load it inside ``arch_init_irq()``. > + > +Required properties > +------------------- > +* compatible: Should be **"mti,cpu-interrupt-controller"** If you wanted to add bindings, please use DT schema format (see writing-schema, writing-bindings and example-schema files). Best regards, Krzysztof