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Date:   Fri, 20 May 2022 19:59:05 +0300
From:   Boris Lysov <arz65xx@gmail.com>
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     arzamas-16@mail.ee, mturquette@baylibre.com, sboyd@kernel.org,
        matthias.bgg@gmail.com, wenst@chromium.org,
        miles.chen@mediatek.com, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org
Subject: Re: [PATCH] clk: mediatek: Fix unused 'ops' field in mtk_pll_data
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On Fri, 20 May 2022 10:27:45 +0200
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote:

> Il 19/05/22 21:27, Boris Lysov ha scritto:
> > Hello, Angelo!
> > 
> > On Wed, 18 May 2022 14:15:13 +0200
> > AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote:
> > 
> >> Il 15/05/22 14:24, Boris Lysov ha scritto:
> >>> From: Boris Lysov <arzamas-16@mail.ee>
> >>>
> >>> Allow to specify optional clk_ops in mtk_pll_data which will be picked up
> >>> in mtk_clk_register_pll. So far no already supported Mediatek SoC needs
> >>> non-default clk_ops for PLLs but instead of removing this field it will be
> >>> actually used in the future for supporting older SoCs (see [1] for
> >>> details) with quirky PLLs.
> >>
> >> { snip }
> > 
> >> Also, if it's just about a bit inversion and a bigger delay:
> >> 1. Bigger delay: Depending on how bigger, we may simply delay more by
> >> default for all PLLs, even the ones that aren't requiring us to wait for
> >> longer... ...after all, if it's about waiting for 10/20 *microseconds* more
> >> { snip }
> > 
> > According to the mt6577 datasheet the largest settling time is 10
> > *milli*seconds for AUDPLL [1]. In my opinion this is way too much to be set
> > as default for all mediatek devices.
> > 
> 
> { snip } Perhaps we should look into that AUDPLL matter later, as audio is one
> kind of functionality that you want to enable in the immediate term
Not gonna lie, I also though so about TVDDS, too. Because considering how
unimportant AUDPLL and TVDDS are for basic system usability, I'd rather not put
effort into them at first stages. Afaik, TVDDS is barely used even in the
genuine downstream code!
I just didn't know if it would be okay to make partial PLL support. But now...
> The top clocks should have most of the PLLs, but you can avoid adding some
> that are a bit problematic, such as that AUDPLL that you were talking
> about... in my opinion, at least, it's not a big deal if we add these PLLs
> later when enabling more functionality
...I understand, thanks!

> - I agree it's a nice to have, but bringing up the platform comes first, and
> this means the top clock controllers and eventually multimedia (to get a
> display up!).
> { snip } Try upstreaming the top, very necessary, clocks to achieve a full
> console boot, as this gives you a good chance to start landing some solid and
> critical base for your platform.
In case of (at least some) mt6577 devices a full console boot is possible even
without the clock driver thanks to the work preloader and Uboot do on that
matter. If you open https://github.com/arzam16/linux-mt6577 you will see that
with fixed-clocks in dts it's possible to start a framebuffer console and even a
simple game!
On the other hand, I believe implementing a proper mainline clock driver is a
must for further development. Hoping for the ancient UBoot filled to the brim
with proprietary components to do all the work is not the best idea.

> >> 2. Bit inversion: that can be solved simply with a flag in the
> >> prepare/unprepare ops for this driver... and if you want something that
> >> performs even better, sparing you a nanosecond or two, you can always
> >> assign an "inverted" callback for managing that single bit;
> > 
> > Not all mt6577 PLLs need bit inversion. 2 PLLs follow the common flow (set a
> > CON0_PWR_ON bit to start). 6 PLLs set this bit to 0 to start. And 1 PLL
> > (which is actually a DDS) needs to write a magic value to specific register
> > (in apmixed region) to start.
> 
> That's interesting.
> { snip }
> The top clocks should have most of the PLLs, but you can avoid adding some
> that are a bit problematic, such as that AUDPLL that you were talking
> about... in my opinion, at least, it's not a big deal if we add these PLLs
> later when enabling more functionality: that will give you the chance to add
> the PLLs that are in need of that "enable bit inversion" logic which, from
> what I understand from your words, covers 6 to 8 PLLs.
To put it clear: there are 9 PLLs in mt6577 in total:
1. ARMPLL - write 0 to enable (need bit inversion), important PLL
2. MAINPLL - write 0 to enable (need bit inv.), important PLL
3. IPLL - write 0 to enable (need bit inv.), for "image sensing" subsystem
4. UPLL - write 0 to enable (need bit inv.), not sure what it's for
5. MDPLL - write 0 to enable (need bit inv.), for "modem" subsystem
6. TVDDS - write magic value to enable, for TV-related IP and HDMI
7. WPLL - write 1 to enable, for "modem" subsystem
8. AUDPLL - write 1 to enable, for "audio" subsystem
9. MEMPLL - write 0 to enable (need bit inv.), for "ddr" subsystem
As you can see, the most important PLLs (ARM and MAIN) need bit inversion and
is why I decided to use 'ops' field. 

> That's a lot, because that makes you able to
> add all of the clocks that are in infra, top, mfg, apmixed: like that, you're
> also getting most of the IP up (timers, i2c, spi, mtk-sd for your eMMC/uSD).
Here's where it gets interesting. Afaiu mainline kernel expects me to provide
all the info on the clock heirarchy. In my case it's almost impossible to figure
out any relation between the PLLs and MUXes and clocks. mt6577 datasheet
doesn't have any meaningful clock hierarchy diagrams unlike more modern SoCs.
The downstream code works in a "fire everything up on boot and don't care" way,
it relies on undocumented registers for clock management and also doesn't have
any sane clues to figure out the hierarchy. Even the frequency of the core
fixed clock is not known clearly - it's either 13 or 26 or 260 MHz -
downstream code doesn't give the exact answer (my mainline kernel works fine
with 13 MHz, though).

This is going to be *hell* to implement in mainline. Related: [1]

[1] https://www.spinics.net/lists/linux-clk/msg65449.html