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[188.217.53.154]) by smtp.gmail.com with ESMTPSA id g24-20020adfa498000000b0020c5253d90csm9159068wrb.88.2022.05.22.23.57.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 May 2022 23:57:56 -0700 (PDT) Date: Mon, 23 May 2022 08:57:54 +0200 From: Tommaso Merciai To: Andrew Lunn Cc: michael@amarulasolutions.com, alberto.bianchi@amarulasolutions.com, linux-amarula@amarulasolutions.com, linuxfancy@googlegroups.com, Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii Message-ID: <20220523065754.GJ1589864@tom-ThinkPad-T14s-Gen-2i> References: <20220520235846.1919954-1-tommaso.merciai@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, May 21, 2022 at 08:39:02PM +0200, Andrew Lunn wrote: > On Sat, May 21, 2022 at 01:58:46AM +0200, Tommaso Merciai wrote: > > RGMII mode can be enable from dp83822 straps, and also writing bit 9 > > of register 0x17 - RMII and Status Register (RCSR). > > When phy_interface_is_rgmii rgmii mode must be enabled, same for > > contrary, this prevents malconfigurations of hw straps > > > > References: > > - https://www.ti.com/lit/gpn/dp83822i p66 > > > > Signed-off-by: Tommaso Merciai > > Co-developed-by: Michael Trimarchi > > Suggested-by: Alberto Bianchi > > Tested-by: Tommaso Merciai > > Reviewed-by: Andrew Lunn > > If you want to, you could go further. If bit 9 is clear, bit 5 defines > the mode, either RMII or MII. There are interface modes defined for > these, so you could get bit 5 as well. Hi Andrew, Thanks for the review and for your time. I'll try to go further, like you suggest :) Regards, Tommaso > > Andrew -- Tommaso Merciai Embedded Linux Engineer tommaso.merciai@amarulasolutions.com __________________________________ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 info@amarulasolutions.com www.amarulasolutions.com