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Date:   Mon, 23 May 2022 13:30:06 +0300
From:   Serge Semin <fancer.lancer@gmail.com>
To:     Marc Zyngier <maz@kernel.org>,
        Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>
Cc:     Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Paul Burton <paulburton@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        Chao-ying Fu <cfu@wavecomp.com>
Subject: Re: [PATCH 03/12] irqchip: mips-gic: Introduce
 gic_with_each_online_cpu()
Message-ID: <20220523103006.gklftp22pyjrkoqm@mobilestation>
References: <20220519185125.11686-1-Dragan.Mladjenovic@syrmia.com>
 <20220519185125.11686-4-Dragan.Mladjenovic@syrmia.com>
 <87k0agmwdc.wl-maz@kernel.org>
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On Fri, May 20, 2022 at 09:38:55AM +0100, Marc Zyngier wrote:
> On Thu, 19 May 2022 19:51:16 +0100,
> Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com> wrote:
> > 
> > From: Paul Burton <paulburton@kernel.org>
> > 
> > A few pieces of code in the MIPS GIC driver operate on the GIC local
> > register block for each online CPU, accessing each via the GIC's
> > other/redirect register block. This patch abstracts the process of
> > iterating over online CPUs & configuring the other/redirect region to
> > access their registers through a new gic_with_each_online_cpu() macro.
> > 
> > This simplifies users of the new macro slightly, and more importantly
> > prepares us for handling multi-cluster systems where the register
> > configuration will be done via the CM's GCR_CL_REDIRECT register. By
> > abstracting all other/redirect block configuration through this macro,
> > and the __gic_with_next_online_cpu() function which backs it, users will
> > trivially gain support for multi-cluster when it is implemented in
> > __gic_with_next_online_cpu().
> > 
> > Signed-off-by: Paul Burton <paulburton@kernel.org>
> > Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
> > 
> > diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> > index ff89b36267dd..4872bebe24cf 100644
> > --- a/drivers/irqchip/irq-mips-gic.c
> > +++ b/drivers/irqchip/irq-mips-gic.c
> 

> No SoB from the sender, odd patch format (no ---), and I didn't get a
> complete series, which makes it impossible to review things in context
> (I don't even know what the series is about).

Hi Marc,
Here is the link to the whole series:
https://lore.kernel.org/linux-mips/20220519185125.11686-1-Dragan.Mladjenovic@syrmia.com/
but yes, having a full patchset in the inbox would be much better.

@Dragan, if you are still willing to get the series reviewed, please
add both Marc and me to the lists of the recipients of each patch and
resend. Of course make sure Thomas Bogendoerfer gets the whole series too.

@Dragan, as Marc already noted the sender's SoB must be added.
Who is Chao-ying and why do you need to add his SoB to each patch?
For instance you have the patch
"[PATCH 05/12] irqchip: mips-gic: Setup defaults in each cluster"
in this series which is stated being authored by Chao-ying but
you've also added Paul' SoB there. What did Paul do for that patch
development?

-Sergey

> 
> Please fix things and resend.
> 
> 	M.
> 
> -- 
> Without deviation from the norm, progress is not possible.