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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Mon, 23 May 2022 18:28:04 +0100
Message-ID: <CA+V-a8vKNBf78mLzu_RJjj-vWMvw7fAdZ=oA1V--UYYcL2FdnA@mail.gmail.com>
Subject: Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support
To:     Biju Das <biju.das.jz@bp.renesas.com>
Cc:     Andy Shevchenko <andy.shevchenko@gmail.com>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Marc Zyngier <maz@kernel.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Thomas Gleixner <tglx@linutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Thierry Reding <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        linux-tegra <linux-tegra@vger.kernel.org>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Phil Edworthy <phil.edworthy@renesas.com>
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Hi Biju,

On Thu, May 19, 2022 at 7:58 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > Subject: Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support
> >
> > On Wed, May 18, 2022 at 10:10 PM Andy Shevchenko
> > <andy.shevchenko@gmail.com> wrote:
> > >
> > > On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > >
> > > > Hi All,
> > > >
> > > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> > > > Renesas RZ/G2L SoC's with below pins:
> > > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI
> > > >   interrupts
> > > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
> > > >   maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> > > > - NMI edge select.
> > > >
> > > >
> > _____________
> > > >                                                              |    GIC
> > |
> > > >                                                              |
> > ________  |
> > > >                                       ____________           | |
> > | |
> > > > NMI --------------------------------->|          |  SPI0-479 | | GIC-
> > 600| |
> > > >              _______                  |          |------------>|
> > | |
> > > >              |      |                 |          |  PPI16-31 | |
> > | |
> > > >              |      | IRQ0-IRQ7       |   IRQC   |------------>|
> > | |
> > > > P0_P48_4 --->| GPIO |---------------->|          |           |
> > |________| |
> > > >              |      |GPIOINT0-122     |          |           |
> > |
> > > >              |      |---------------->| TINT0-31 |           |
> > |
> > > >              |______|                 |__________|
> > |____________|
> > > >
> > > > The proposed patches add hierarchical IRQ domain, one in IRQC driver
> > > > and another in pinctrl driver. Upon interrupt requests map the
> > > > interrupt to GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC
> > > > SPI, this mapping is handled by the pinctrl and IRQC driver.
> > >
> > > Where is the explanation on why valid_mask can't be used instead?
> > >
> > The .valid_mask option is one time setting
>
> One question, if it is one time setting, Is it possible to use .valid mask to invalidate
> invalid gpio lines?(ie, currently gpio range is 392, but there is only 123 GPIOs
> present in the SoC, not sure this call back can be used to invalidate the non-supported GPIOS??).
>
Yes can be added, I will include it in the next version.

Cheers,
Prabhakar