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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v8-20020a17090331c800b0015d1a662ad2si14408780ple.241.2022.05.25.09.12.05; Wed, 25 May 2022 09:12:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Zu8BQxKJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245277AbiEYPtO (ORCPT + 99 others); Wed, 25 May 2022 11:49:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238194AbiEYPtN (ORCPT ); Wed, 25 May 2022 11:49:13 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A46D934649; Wed, 25 May 2022 08:49:11 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4105A61520; Wed, 25 May 2022 15:49:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7C77C34117; Wed, 25 May 2022 15:49:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653493750; bh=bIicfEgP7s139tN40AgWtxDRRKGzaemz0C3u+wU/Nvo=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Zu8BQxKJOgVnmy8Qd3W+MW8TvMDQ4wUY7ngpChp1UIxpfL9uhVVt7AmSxzd4JIRVd Ji9Fvgy6dUznbLvDkTxuqwrkO5N7YL3xCam3jVmgNGnydVKb7hVhpqCCXJaY7c495S IK4G2F7g3ZgBjVctlZm9TIRCP9vZV1JsLkp2fRDU1hboXSIUN84t7Nb6eaTzxLV96M xCwTTFvnvBJK/rF95CRD2qVJIwbKIbdK51cwThSzPRV8W/CONMHH68ymqCYCZlTxhw V6V1EZWNU/vpu4HuhVdZQUAROSli/+9QCCmq4nQ6swrCPMkGtanlvLnh4Ln9j9oqoP N7khJpD9nlwlg== Received: by mail-oi1-f181.google.com with SMTP id i66so25453118oia.11; Wed, 25 May 2022 08:49:10 -0700 (PDT) X-Gm-Message-State: AOAM532bIn9/AHRJ4hZppAypfZYSOLtCJ0VoO0VvTCElxEGsCf0+ueb5 8JqCqDqdEOlWfVJ2Nziv21K1d9g32SHfu2Ifii4= X-Received: by 2002:a05:6808:e8d:b0:322:bac0:2943 with SMTP id k13-20020a0568080e8d00b00322bac02943mr5701111oil.126.1653493749757; Wed, 25 May 2022 08:49:09 -0700 (PDT) MIME-Version: 1.0 References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> <20220525151106.2176147-6-sunilvl@ventanamicro.com> In-Reply-To: <20220525151106.2176147-6-sunilvl@ventanamicro.com> From: Ard Biesheuvel Date: Wed, 25 May 2022 17:48:58 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 5/5] riscv/efi_stub: Support for 64bit boot-hartid To: Sunil V L Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel , linux-riscv , Linux Kernel Mailing List , linux-efi , Sunil V L Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 25 May 2022 at 17:11, Sunil V L wrote: > > The boot-hartid can be a 64bit value on RV64 platforms. Currently, > the "boot-hartid" in DT is assumed to be 32bit only. This patch > detects the size of the "boot-hartid" and uses 32bit or 64bit > FDT reads appropriately. > > Signed-off-by: Sunil V L > --- > drivers/firmware/efi/libstub/riscv-stub.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/firmware/efi/libstub/riscv-stub.c b/drivers/firmware/efi/libstub/riscv-stub.c > index 9e85e58d1f27..d748533f1329 100644 > --- a/drivers/firmware/efi/libstub/riscv-stub.c > +++ b/drivers/firmware/efi/libstub/riscv-stub.c > @@ -29,7 +29,7 @@ static int get_boot_hartid_from_fdt(void) > { > const void *fdt; > int chosen_node, len; > - const fdt32_t *prop; > + const void *prop; > > fdt = get_efi_config_table(DEVICE_TREE_GUID); > if (!fdt) > @@ -40,10 +40,16 @@ static int get_boot_hartid_from_fdt(void) > return -EINVAL; > > prop = fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); > - if (!prop || len != sizeof(u32)) > + if (!prop) > + return -EINVAL; > + > + if (len == sizeof(u32)) > + hartid = (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); > + else if (len == sizeof(u64)) > + hartid = (unsigned long) fdt64_to_cpu(*(fdt64_t *)prop); Does RISC-V care about alignment? A 64-bit quantity is not guaranteed to appear 64-bit aligned in the DT, and the cast violates C alignment rules, so this should probably used get_unaligned_be64() or something like that. > + else > return -EINVAL; > > - hartid = fdt32_to_cpu(*prop); > return 0; > } > > -- > 2.25.1 >