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Date:   Thu, 26 May 2022 03:57:20 -0700
From:   Piyush Malgujar <pmalgujar@marvell.com>
To:     Andrew Lunn <andrew@lunn.ch>
CC:     "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Chandrakala Chavva" <cchavva@marvell.com>,
        Damian Eppel <deppel@marvell.com>,
        "Heiner Kallweit" <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        "David S. Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        "Paolo Abeni" <pabeni@redhat.com>
Subject: Re: [PATCH] Marvell MDIO clock related changes.
Message-ID: <20220526105720.GA4922@Dell2s-9>
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On Fri, Apr 29, 2022 at 04:24:53PM +0200, Andrew Lunn wrote:
> > > > 2) Marvell MDIO clock frequency attribute change:
> > > > This MDIO change provides an option for user to have the bus speed set
> > > > to their needs which is otherwise set to default(3.125 MHz).
> > > 
> > > Please read 802.3 Clause 22. The default should be 2.5MHz.
> > > 
> > 
> > These changes are only specific to Marvell Octeon family.
> 
> Are you saying the Marvell Octeon family decide to ignore 802.3?  Have
> you tested every possible PHY that could be connected to this MDIO bus
> and they all work for 3.125MHz, even though 802.3 says they only need
> to support up to 2.5Mhz?
> 
>      Andrew

Hi Andrew,

Yes, but as for Marvell Octeon family it defaults to 3.125 MHz and this
driver is already existing in the kernel.
This patch is not changing that, only adding support to configure
clock-freq from DTS.
Also, following PHYs have been verified with it:
PHY_MARVELL_88E1548,
PHY_MARVELL_5123,
PHY_MARVELL_5113,
PHY_MARVELL_6141,
PHY_MARVELL_88E1514,
PHY_MARVELL_3310,
PHY_VITESSE_8574

Thanks,
Piyush