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Message-ID: <fe7ca417-6c0f-1558-f5b1-a5ebc31e93c1@flygoat.com>
Date:   Wed, 25 May 2022 19:33:03 +0100
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Subject: Re: [PATCH v2 02/12] MIPS: GIC: Generate redirect block accessors
Content-Language: en-GB
To:     Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc:     Chao-ying Fu <cfu@wavecomp.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Geert Uytterhoeven <geert@linux-m68k.org>,
        Greg Ungerer <gerg@kernel.org>,
        Hauke Mehrtens <hauke@hauke-m.de>,
        Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
        linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
        Marc Zyngier <maz@kernel.org>,
        Paul Burton <paulburton@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Serge Semin <fancer.lancer@gmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Tiezhu Yang <yangtiezhu@loongson.cn>
References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com>
 <20220525121030.16054-3-Dragan.Mladjenovic@syrmia.com>
From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
In-Reply-To: <20220525121030.16054-3-Dragan.Mladjenovic@syrmia.com>
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在 2022/5/25 13:10, Dragan Mladjenovic 写道:
> From: Paul Burton <paulburton@kernel.org>
>
> With CM 3.5 the "core-other" register block evolves into the "redirect"
> register block, which is capable of accessing not only the core local
> registers of other cores but also the shared/global registers of other
> clusters.
>
> This patch generates accessor functions for shared/global registers
> accessed via the redirect block, with "redir_" inserted after "gic_" in
> their names. For example the accessor function:
>
>    read_gic_config()
>
> ...accesses the GIC_CONFIG register of the GIC in the local cluster.
> With this patch a new function:
>
>    read_gic_redir_config()
>
> ...is added which accesses the GIC_CONFIG register of the GIC in
> whichever cluster the GCR_CL_REDIRECT register is configured to access.
>
> This mirrors the similar redirect block accessors already provided for
> the CM & CPC.
>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Checked against I6500 system programming manual.

Thanks.
- Jiaxun
>
> diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h
> index 084cac1c5ea2..fd9da5e3beaa 100644
> --- a/arch/mips/include/asm/mips-gic.h
> +++ b/arch/mips/include/asm/mips-gic.h
> @@ -28,11 +28,13 @@ extern void __iomem *mips_gic_base;
>   
>   /* For read-only shared registers */
>   #define GIC_ACCESSOR_RO(sz, off, name)					\
> -	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
> +	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)	\
> +	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
>   
>   /* For read-write shared registers */
>   #define GIC_ACCESSOR_RW(sz, off, name)					\
> -	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
> +	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)	\
> +	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
>   
>   /* For read-only local registers */
>   #define GIC_VX_ACCESSOR_RO(sz, off, name)				\
> @@ -45,7 +47,7 @@ extern void __iomem *mips_gic_base;
>   	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
>   
>   /* For read-only shared per-interrupt registers */
> -#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)			\
> +#define _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)		\
>   static inline void __iomem *addr_gic_##name(unsigned int intr)		\
>   {									\
>   	return mips_gic_base + (off) + (intr * (stride));		\
> @@ -58,8 +60,8 @@ static inline unsigned int read_gic_##name(unsigned int intr)		\
>   }
>   
>   /* For read-write shared per-interrupt registers */
> -#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name)			\
> -	GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)			\
> +#define _GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name)		\
> +	_GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)		\
>   									\
>   static inline void write_gic_##name(unsigned int intr,			\
>   				    unsigned int val)			\
> @@ -68,22 +70,30 @@ static inline void write_gic_##name(unsigned int intr,			\
>   	__raw_writel(val, addr_gic_##name(intr));			\
>   }
>   
> +#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)			\
> +	_GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)		\
> +	_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name)
> +
> +#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name)			\
> +	_GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name)		\
> +	_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name)
> +
>   /* For read-only local per-interrupt registers */
>   #define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name)		\
> -	GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,		\
> +	_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,		\
>   				 stride, vl_##name)			\
> -	GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,		\
> +	_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,		\
>   				 stride, vo_##name)
>   
>   /* For read-write local per-interrupt registers */
>   #define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name)		\
> -	GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,		\
> +	_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,		\
>   				 stride, vl_##name)			\
> -	GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,		\
> +	_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,		\
>   				 stride, vo_##name)
>   
>   /* For read-only shared bit-per-interrupt registers */
> -#define GIC_ACCESSOR_RO_INTR_BIT(off, name)				\
> +#define _GIC_ACCESSOR_RO_INTR_BIT(off, name)				\
>   static inline void __iomem *addr_gic_##name(void)			\
>   {									\
>   	return mips_gic_base + (off);					\
> @@ -106,8 +116,8 @@ static inline unsigned int read_gic_##name(unsigned int intr)		\
>   }
>   
>   /* For read-write shared bit-per-interrupt registers */
> -#define GIC_ACCESSOR_RW_INTR_BIT(off, name)				\
> -	GIC_ACCESSOR_RO_INTR_BIT(off, name)				\
> +#define _GIC_ACCESSOR_RW_INTR_BIT(off, name)				\
> +	_GIC_ACCESSOR_RO_INTR_BIT(off, name)				\
>   									\
>   static inline void write_gic_##name(unsigned int intr)			\
>   {									\
> @@ -146,6 +156,14 @@ static inline void change_gic_##name(unsigned int intr,			\
>   	}								\
>   }
>   
> +#define GIC_ACCESSOR_RO_INTR_BIT(off, name)				\
> +	_GIC_ACCESSOR_RO_INTR_BIT(off, name)				\
> +	_GIC_ACCESSOR_RO_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name)
> +
> +#define GIC_ACCESSOR_RW_INTR_BIT(off, name)				\
> +	_GIC_ACCESSOR_RW_INTR_BIT(off, name)				\
> +	_GIC_ACCESSOR_RW_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name)
> +
>   /* For read-only local bit-per-interrupt registers */
>   #define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name)			\
>   	GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,		\
> @@ -155,10 +173,10 @@ static inline void change_gic_##name(unsigned int intr,			\
>   
>   /* For read-write local bit-per-interrupt registers */
>   #define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name)			\
> -	GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,		\
> -				 vl_##name)				\
> -	GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off,		\
> -				 vo_##name)
> +	_GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,		\
> +				  vl_##name)				\
> +	_GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off,		\
> +				  vo_##name)
>   
>   /* GIC_SH_CONFIG - Information about the GIC configuration */
>   GIC_ACCESSOR_RW(32, 0x000, config)