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[131.111.5.141]) by smtp.gmail.com with ESMTPSA id d23-20020a1c7317000000b0039736892653sm117725wmb.27.2022.05.25.16.36.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 May 2022 16:36:25 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3696.80.82.1.1\)) Subject: Re: [PATCH 5/5] riscv/efi_stub: Support for 64bit boot-hartid From: Jessica Clarke In-Reply-To: Date: Thu, 26 May 2022 00:36:24 +0100 Cc: Heinrich Schuchardt , Ard Biesheuvel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Atish Patra , Anup Patel , linux-riscv , Linux Kernel Mailing List , linux-efi , Sunil V L , Sunil V L Content-Transfer-Encoding: quoted-printable Message-Id: <5829932A-6E45-46CA-AADA-14EDD903C4AD@jrtc27.com> References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> <20220525151106.2176147-6-sunilvl@ventanamicro.com> <1e90b15b-8c73-0de8-2885-1292923b7575@canonical.com> To: Atish Patra X-Mailer: Apple Mail (2.3696.80.82.1.1) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26 May 2022, at 00:11, Atish Patra wrote: >=20 > On Wed, May 25, 2022 at 9:09 AM Heinrich Schuchardt > wrote: >>=20 >> On 5/25/22 17:48, Ard Biesheuvel wrote: >>> On Wed, 25 May 2022 at 17:11, Sunil V L = wrote: >>>>=20 >>>> The boot-hartid can be a 64bit value on RV64 platforms. Currently, >>>> the "boot-hartid" in DT is assumed to be 32bit only. This patch >>>> detects the size of the "boot-hartid" and uses 32bit or 64bit >>>> FDT reads appropriately. >>>>=20 >>>> Signed-off-by: Sunil V L >>>> --- >>>> drivers/firmware/efi/libstub/riscv-stub.c | 12 +++++++++--- >>>> 1 file changed, 9 insertions(+), 3 deletions(-) >>>>=20 >>>> diff --git a/drivers/firmware/efi/libstub/riscv-stub.c = b/drivers/firmware/efi/libstub/riscv-stub.c >>>> index 9e85e58d1f27..d748533f1329 100644 >>>> --- a/drivers/firmware/efi/libstub/riscv-stub.c >>>> +++ b/drivers/firmware/efi/libstub/riscv-stub.c >>>> @@ -29,7 +29,7 @@ static int get_boot_hartid_from_fdt(void) >>>> { >>>> const void *fdt; >>>> int chosen_node, len; >>>> - const fdt32_t *prop; >>>> + const void *prop; >>>>=20 >>>> fdt =3D get_efi_config_table(DEVICE_TREE_GUID); >>>> if (!fdt) >>>> @@ -40,10 +40,16 @@ static int get_boot_hartid_from_fdt(void) >>>> return -EINVAL; >>>>=20 >>>> prop =3D fdt_getprop((void *)fdt, chosen_node, "boot-hartid", = &len); >>>> - if (!prop || len !=3D sizeof(u32)) >>>> + if (!prop) >>>> + return -EINVAL; >>>> + >>>> + if (len =3D=3D sizeof(u32)) >>>> + hartid =3D (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); >>>> + else if (len =3D=3D sizeof(u64)) >>>> + hartid =3D (unsigned long) fdt64_to_cpu(*(fdt64_t *)prop); >>>=20 >>> Does RISC-V care about alignment? A 64-bit quantity is not = guaranteed >>> to appear 64-bit aligned in the DT, and the cast violates C = alignment >>> rules, so this should probably used get_unaligned_be64() or = something >>> like that. >>=20 >> When running in S-mode the SBI handles unaligned access but this has = a >> performance penalty. >>=20 >> We could use fdt64_to_cpu(__get_unaligned_t(fdt64_t, prop)) here. >>=20 >=20 > It is better to avoid unaligned access in the kernel. There are some > plans to disable > misaligned load/store emulation in the firmware if user space requests > it via prctl. Why? Jess > We need another SBI extension to do that. The idea is to keep it > enabled by default in the firmware but > userspace should have an option to disable it via prctl. If we make > sure that the kernel doesn't invoke any > unaligned access, this feature can be implemented easily. >=20 >> Best regards >>=20 >> Heinrich >>=20 >>>=20 >>>=20 >>>> + else >>>> return -EINVAL; >>>>=20 >>>> - hartid =3D fdt32_to_cpu(*prop); >>>> return 0; >>>> } >>>>=20 >>>> -- >>>> 2.25.1 >>>>=20 >>=20 >=20 >=20 > --=20 > Regards, > Atish >=20 > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv