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From:   Atish Patra <atishp@atishpatra.org>
Date:   Thu, 26 May 2022 16:10:51 -0700
Message-ID: <CAOnJCU+eutRHEEgXi8od+xY+0AyWj117MDwjY-hFVO3ZDjf1bg@mail.gmail.com>
Subject: Re: [PATCH V2 4/5] riscv: cpu: Support for 64bit hartid
To:     Sunil V L <sunilvl@ventanamicro.com>
Cc:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ard Biesheuvel <ardb@kernel.org>,
        Marc Zyngier <maz@kernel.org>,
        Atish Patra <atishp@rivosinc.com>,
        Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
        Anup Patel <apatel@ventanamicro.com>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        linux-efi <linux-efi@vger.kernel.org>,
        Sunil V L <sunil.vl@gmail.com>
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On Thu, May 26, 2022 at 3:12 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> Adds support for 64bit hartid in riscv_of_processor_hartid()

The commit text is a bit misleading as you are adding support for XLEN
hartid. For RV32, it is still 32bit.
This applies to the entire series.

>   - Separate return value and status code.
>   - Make hartid variable type as unsigned long.
>   - Update the callers.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  arch/riscv/include/asm/processor.h |  4 ++--
>  arch/riscv/kernel/cpu.c            | 26 +++++++++++++++-----------
>  arch/riscv/kernel/cpufeature.c     |  6 ++++--
>  arch/riscv/kernel/smpboot.c        |  9 +++++----
>  drivers/clocksource/timer-riscv.c  | 15 ++++++++-------
>  drivers/irqchip/irq-riscv-intc.c   |  7 ++++---
>  drivers/irqchip/irq-sifive-plic.c  |  7 ++++---
>  7 files changed, 42 insertions(+), 32 deletions(-)
>
> diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> index 0749924d9e55..99fae9398506 100644
> --- a/arch/riscv/include/asm/processor.h
> +++ b/arch/riscv/include/asm/processor.h
> @@ -75,8 +75,8 @@ static inline void wait_for_interrupt(void)
>  }
>
>  struct device_node;
> -int riscv_of_processor_hartid(struct device_node *node);
> -int riscv_of_parent_hartid(struct device_node *node);
> +int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
> +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
>
>  extern void riscv_fill_hwcap(void);
>  extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index ccb617791e56..477a33b34c95 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -14,37 +14,36 @@
>   * Returns the hart ID of the given device tree node, or -ENODEV if the node
>   * isn't an enabled and valid RISC-V hart node.
>   */
> -int riscv_of_processor_hartid(struct device_node *node)
> +int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
>  {
>         const char *isa;
> -       u32 hart;
>
>         if (!of_device_is_compatible(node, "riscv")) {
>                 pr_warn("Found incompatible CPU\n");
>                 return -ENODEV;
>         }
>
> -       hart = of_get_cpu_hwid(node, 0);
> -       if (hart == ~0U) {
> +       *hart = (unsigned long) of_get_cpu_hwid(node, 0);
> +       if (*hart == ~0UL) {
>                 pr_warn("Found CPU without hart ID\n");
>                 return -ENODEV;
>         }
>
>         if (!of_device_is_available(node)) {
> -               pr_info("CPU with hartid=%d is not available\n", hart);
> +               pr_info("CPU with hartid=%lu is not available\n", *hart);
>                 return -ENODEV;
>         }
>
>         if (of_property_read_string(node, "riscv,isa", &isa)) {
> -               pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart);
> +               pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
>                 return -ENODEV;
>         }
>         if (isa[0] != 'r' || isa[1] != 'v') {
> -               pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa);
> +               pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
>                 return -ENODEV;
>         }
>
> -       return hart;
> +       return 0;
>  }
>
>  /*
> @@ -53,11 +52,16 @@ int riscv_of_processor_hartid(struct device_node *node)
>   * To achieve this, we walk up the DT tree until we find an active
>   * RISC-V core (HART) node and extract the cpuid from it.
>   */
> -int riscv_of_parent_hartid(struct device_node *node)
> +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
>  {
> +       int rc;
> +
>         for (; node; node = node->parent) {
> -               if (of_device_is_compatible(node, "riscv"))
> -                       return riscv_of_processor_hartid(node);
> +               if (of_device_is_compatible(node, "riscv")) {
> +                       rc = riscv_of_processor_hartid(node, hartid);
> +                       if (!rc)
> +                               return 0;
> +               }
>         }
>
>         return -1;
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 1b2d42d7f589..49c05bd9352d 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -67,8 +67,9 @@ void __init riscv_fill_hwcap(void)
>         struct device_node *node;
>         const char *isa;
>         char print_str[NUM_ALPHA_EXTS + 1];
> -       int i, j;
> +       int i, j, rc;
>         static unsigned long isa2hwcap[256] = {0};
> +       unsigned long hartid;
>
>         isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
>         isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
> @@ -86,7 +87,8 @@ void __init riscv_fill_hwcap(void)
>                 DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
>                 const char *temp;
>
> -               if (riscv_of_processor_hartid(node) < 0)
> +               rc = riscv_of_processor_hartid(node, &hartid);
> +               if (rc < 0)
>                         continue;
>
>                 if (of_property_read_string(node, "riscv,isa", &isa)) {
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index 622f226454d5..4336610a19ee 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -76,15 +76,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
>  void __init setup_smp(void)
>  {
>         struct device_node *dn;
> -       int hart;
> +       unsigned long hart;
>         bool found_boot_cpu = false;
>         int cpuid = 1;
> +       int rc;
>
>         cpu_set_ops(0);
>
>         for_each_of_cpu_node(dn) {
> -               hart = riscv_of_processor_hartid(dn);
> -               if (hart < 0)
> +               rc = riscv_of_processor_hartid(dn, &hart);
> +               if (rc < 0)
>                         continue;
>
>                 if (hart == cpuid_to_hartid_map(0)) {
> @@ -94,7 +95,7 @@ void __init setup_smp(void)
>                         continue;
>                 }
>                 if (cpuid >= NR_CPUS) {
> -                       pr_warn("Invalid cpuid [%d] for hartid [%d]\n",
> +                       pr_warn("Invalid cpuid [%d] for hartid [%lu]\n",
>                                 cpuid, hart);
>                         continue;
>                 }
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 1767f8bf2013..55142c27f0bc 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -101,20 +101,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
>
>  static int __init riscv_timer_init_dt(struct device_node *n)
>  {
> -       int cpuid, hartid, error;
> +       int cpuid, error;
> +       unsigned long hartid;
>         struct device_node *child;
>         struct irq_domain *domain;
>
> -       hartid = riscv_of_processor_hartid(n);
> -       if (hartid < 0) {
> -               pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
> +       error = riscv_of_processor_hartid(n, &hartid);
> +       if (error < 0) {
> +               pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
>                         n, hartid);
> -               return hartid;
> +               return error;
>         }
>
>         cpuid = riscv_hartid_to_cpuid(hartid);
>         if (cpuid < 0) {
> -               pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
> +               pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
>                 return cpuid;
>         }
>
> @@ -140,7 +141,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>                 return -ENODEV;
>         }
>
> -       pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
> +       pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
>                __func__, cpuid, hartid);
>         error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
>         if (error) {
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index b65bd8878d4f..499e5f81b3fe 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -95,10 +95,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = {
>  static int __init riscv_intc_init(struct device_node *node,
>                                   struct device_node *parent)
>  {
> -       int rc, hartid;
> +       int rc;
> +       unsigned long hartid;
>
> -       hartid = riscv_of_parent_hartid(node);
> -       if (hartid < 0) {
> +       rc = riscv_of_parent_hartid(node, &hartid);
> +       if (rc < 0) {
>                 pr_warn("unable to find hart id for %pOF\n", node);
>                 return 0;
>         }
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index bb87e4c3b88e..4710d9741f36 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -317,7 +317,8 @@ static int __init plic_init(struct device_node *node,
>         for (i = 0; i < nr_contexts; i++) {
>                 struct of_phandle_args parent;
>                 irq_hw_number_t hwirq;
> -               int cpu, hartid;
> +               int cpu;
> +               unsigned long hartid;
>
>                 if (of_irq_parse_one(node, i, &parent)) {
>                         pr_err("failed to parse parent for context %d.\n", i);
> @@ -341,8 +342,8 @@ static int __init plic_init(struct device_node *node,
>                         continue;
>                 }
>
> -               hartid = riscv_of_parent_hartid(parent.np);
> -               if (hartid < 0) {
> +               error = riscv_of_parent_hartid(parent.np, &hartid);
> +               if (error < 0) {
>                         pr_warn("failed to parse hart ID for context %d.\n", i);
>                         continue;
>                 }
> --
> 2.25.1
>

Otherwise, it looks good.

Reviewed-by: Atish Patra <atishp@rivosinc.com>

-- 
Regards,
Atish