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Date:   Thu, 26 May 2022 12:49:03 -0300
From:   Arnaldo Carvalho de Melo <acme@kernel.org>
To:     Ravi Bangoria <ravi.bangoria@amd.com>
Cc:     irogers@google.com, peterz@infradead.org, rrichter@amd.com,
        mingo@redhat.com, mark.rutland@arm.com, jolsa@kernel.org,
        namhyung@kernel.org, tglx@linutronix.de, bp@alien8.de,
        james.clark@arm.com, leo.yan@linaro.org, kan.liang@linux.intel.com,
        ak@linux.intel.com, eranian@google.com, like.xu.linux@gmail.com,
        x86@kernel.org, linux-perf-users@vger.kernel.org,
        linux-kernel@vger.kernel.org, sandipan.das@amd.com,
        ananth.narayan@amd.com, kim.phillips@amd.com,
        santosh.shukla@amd.com
Subject: Re: [PATCH v4 3/5] perf/x86/ibs: Add new IBS register bits into
 header
Message-ID: <Yo+hbx9c/9FoaiJN@kernel.org>
References: <20220523033945.1612-1-ravi.bangoria@amd.com>
 <20220523033945.1612-4-ravi.bangoria@amd.com>
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Em Mon, May 23, 2022 at 09:09:43AM +0530, Ravi Bangoria escreveu:
> IBS support has been enhanced with two new features in upcoming uarch:
> 1. DataSrc extension and 2. L3 miss filtering. Additional set of bits
> has been introduced in IBS registers to exploit these features. Define
> these new bits into arch/x86/ header.

You mentioned the kernel bits were already applied and this was a tools
only series, this one slipped into :-)

- Arnaldo
 
> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
> Acked-by: Ian Rogers <irogers@google.com>
> ---
>  arch/x86/include/asm/amd-ibs.h | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
> index aabdbb5ab920..f3eb098d63d4 100644
> --- a/arch/x86/include/asm/amd-ibs.h
> +++ b/arch/x86/include/asm/amd-ibs.h
> @@ -29,7 +29,10 @@ union ibs_fetch_ctl {
>  			rand_en:1,	/* 57: random tagging enable */
>  			fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
>  					 *      (needs IbsFetchComp) */
> -			reserved:5;	/* 59-63: reserved */
> +			l3_miss_only:1,	/* 59: Collect L3 miss samples only */
> +			fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */
> +			fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */
> +			reserved:2;	/* 62-63: reserved */
>  	};
>  };
>  
> @@ -38,14 +41,14 @@ union ibs_op_ctl {
>  	__u64 val;
>  	struct {
>  		__u64	opmaxcnt:16,	/* 0-15: periodic op max. count */
> -			reserved0:1,	/* 16: reserved */
> +			l3_miss_only:1,	/* 16: Collect L3 miss samples only */
>  			op_en:1,	/* 17: op sampling enable */
>  			op_val:1,	/* 18: op sample valid */
>  			cnt_ctl:1,	/* 19: periodic op counter control */
>  			opmaxcnt_ext:7,	/* 20-26: upper 7 bits of periodic op maximum count */
> -			reserved1:5,	/* 27-31: reserved */
> +			reserved0:5,	/* 27-31: reserved */
>  			opcurcnt:27,	/* 32-58: periodic op counter current count */
> -			reserved2:5;	/* 59-63: reserved */
> +			reserved1:5;	/* 59-63: reserved */
>  	};
>  };
>  
> @@ -71,11 +74,12 @@ union ibs_op_data {
>  union ibs_op_data2 {
>  	__u64 val;
>  	struct {
> -		__u64	data_src:3,	/* 0-2: data source */
> +		__u64	data_src_lo:3,	/* 0-2: data source low */
>  			reserved0:1,	/* 3: reserved */
>  			rmt_node:1,	/* 4: destination node */
>  			cache_hit_st:1,	/* 5: cache hit state */
> -			reserved1:57;	/* 5-63: reserved */
> +			data_src_hi:2,	/* 6-7: data source high */
> +			reserved1:56;	/* 8-63: reserved */
>  	};
>  };
>  
> -- 
> 2.31.1

-- 

- Arnaldo