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Date:   Mon, 30 May 2022 09:07:28 +0200
From:   Pavel Machek <pavel@ucw.cz>
To:     Conor Dooley <conor.dooley@microchip.com>
Cc:     a.zummo@towertech.it, alexandre.belloni@bootlin.com,
        daire.mcnamara@microchip.com, lewis.hanly@microchip.com,
        linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org,
        linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
Message-ID: <20220530070728.GH1363@bug>
References: <20220516082838.3717982-1-conor.dooley@microchip.com>
 <20220516082838.3717982-2-conor.dooley@microchip.com>
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Hi!

> Add support for the built-in RTC on Microchip PolarFire SoC

> +#define CONTROL_UPLOAD_BIT	BIT(5)
> +#define CONTROL_DOWNLOAD_BIT	BIT(6)
> +#define CONTROL_DOWNLOAD_BIT	BIT(6)
> +#define CONTROL_WAKEUP_CLR_BIT	BIT(8)

Dup?

> +static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
> +{
> +	u32 ctrl;
> +
> +	ctrl = readl(rtcdev->base + CONTROL_REG);
> +	ctrl &= ~(CONTROL_STOP_BIT | CONTROL_START_BIT);
> +	ctrl |= CONTROL_START_BIT;
> +	writel(ctrl, rtcdev->base + CONTROL_REG);
> +}

You don't need to clear bit just to set it.

> +	do {
> +		prog = readl(rtcdev->base + CONTROL_REG);
> +		prog &= CONTROL_UPLOAD_BIT;
> +	} while (prog);

Limit to XY iterations?

> +
> +static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
> +{
> +	u32 mode = readl(rtcdev->base + MODE_REG);
> +	u64 time;
> +
> +	mode = readl(rtcdev->base + MODE_REG);

Dup?

> + if (mode & MODE_WAKE_EN) + alrm->enabled = true; + else + alrm->enabled = false; + 

enabled = ()?

Best regards,
										Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html