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From:   Peng Fan <peng.fan@nxp.com>
To:     Ying Liu <victor.liu@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     Abel Vesa <abel.vesa@nxp.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>
Subject: RE: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table
 properly in ->recalc_rate()
Thread-Topic: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table
 properly in ->recalc_rate()
Thread-Index: AQHYcysk8scyJR0TpECnZjgChwVXYq02rbAwgAB1aKA=
Date:   Mon, 30 May 2022 09:08:45 +0000
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> Subject: RE: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table=
 properly
> in ->recalc_rate()
>=20
> > Subject: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table
> > properly in
> > ->recalc_rate()
> >
> > The PLL parameters in rate table should be directly compared with
> > those read from PLL registers instead of the cooked ones.
> >
> > Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
> > Cc: Abel Vesa <abel.vesa@nxp.com>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Sascha Hauer <s.hauer@pengutronix.de>
> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > Cc: NXP Linux Team <linux-imx@nxp.com>
> > Cc: Peng Fan <peng.fan@nxp.com>
> > Signed-off-by: Liu Ying <victor.liu@nxp.com>
>=20
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
>=20
> > ---
> >  drivers/clk/imx/clk-fracn-gppll.c | 24 +++++++++++++-----------
> >  1 file changed, 13 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-fracn-gppll.c
> > b/drivers/clk/imx/clk-fracn-gppll.c
> > index 71c102d950ab..762b07dd5a6d 100644
> > --- a/drivers/clk/imx/clk-fracn-gppll.c
> > +++ b/drivers/clk/imx/clk-fracn-gppll.c
> > @@ -131,18 +131,7 @@ static unsigned long
> > clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
> >  	mfi =3D FIELD_GET(PLL_MFI_MASK, pll_div);
> >
> >  	rdiv =3D FIELD_GET(PLL_RDIV_MASK, pll_div);
> > -	rdiv =3D rdiv + 1;
> >  	odiv =3D FIELD_GET(PLL_ODIV_MASK, pll_div);
> > -	switch (odiv) {
> > -	case 0:
> > -		odiv =3D 2;
> > -		break;
> > -	case 1:
> > -		odiv =3D 3;
> > -		break;
> > -	default:
> > -		break;
> > -	}
> >
> >  	/*
> >  	 * Sometimes, the recalculated rate has deviation due to @@ -160,6
> > +149,19 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct
> > +clk_hw
> > *hw, unsigned lon
> >  	if (rate)
> >  		return (unsigned long)rate;
> >
> > +	rdiv =3D rdiv + 1;

After check more:
According to doc, needs add a check here:
if (!rdiv)
 rdiv =3D rdiv + 1;

Regards,
Peng.
> > +
> > +	switch (odiv) {
> > +	case 0:
> > +		odiv =3D 2;
> > +		break;
> > +	case 1:
> > +		odiv =3D 3;
> > +		break;
> > +	default:
> > +		break;
> > +	}
> > +
> >  	/* Fvco =3D Fref * (MFI + MFN / MFD) */
> >  	fvco =3D fvco * mfi * mfd + fvco * mfn;
> >  	do_div(fvco, mfd * rdiv * odiv);
> > --
> > 2.25.1