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Message-ID: <ddc1462c-be74-420a-6809-c868fa056fa7@codethink.co.uk>
Date:   Sun, 29 May 2022 16:56:44 +0100
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Subject: Re: [V3] PCI: fu740: Drop to 2.5GT/s to fix initial device probing on
 some boards
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To:     "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc:     Alexandre Ghiti <alex@ghiti.fr>, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
        Bjorn Helgaas <bhelgaas@google.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Rob Herring <robh@kernel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Greentime Hu <greentime.hu@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        David Abdurachmanov <david.abdurachmanov@sifive.com>,
        Neill Whillans <neill.whillans@codethink.co.uk>
References: <20220318152430.526320-1-ben.dooks@codethink.co.uk>
 <2442936e-a53e-59bf-488f-95eac26d1252@ghiti.fr>
 <85e864fd-762e-0780-f829-bfbb178ab24e@ghiti.fr>
 <bded4b1e-3404-6bcd-3289-dc8d5b4d713a@codethink.co.uk>
 <alpine.DEB.2.21.2204140048460.9383@angie.orcam.me.uk>
 <3acd20b2-5882-7cc0-8a7b-7b406b768c1c@codethink.co.uk>
 <alpine.DEB.2.21.2205020049130.9383@angie.orcam.me.uk>
From:   Ben Dooks <ben.dooks@codethink.co.uk>
Organization: Codethink Limited.
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On 02/05/2022 12:46, Maciej W. Rozycki wrote:
> Hi Ben,
> 
>>>    Any idea what might be causing it?  I can't see it being explicitly set
>>> or cleared anywhere, be it in U-Boot or Linux, so it must be done by the
>>> device itself depending on something.  And the lack of this capability
>>> seems to me like non-compliance for a multiple-lane, multiple-speed
>>> device.
>>
>> I'll see if we can reproduce this
> 
>   Have you been able to look into it?
> 

I can't see anything obvious from the code, however my SD card image
does not have lspci on it and I have not had time to make a new image
to test.

I wonder if anyone at SiFive can comment on this?

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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