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From:   "Chanho Park" <chanho61.park@samsung.com>
To:     "'Alim Akhtar'" <alim.akhtar@samsung.com>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <linux-scsi@vger.kernel.org>,
        <linux-phy@lists.infradead.org>
Cc:     <devicetree@vger.kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <vkoul@kernel.org>,
        <avri.altman@wdc.com>, <bvanassche@acm.org>,
        <martin.petersen@oracle.com>, <pankaj.dubey@samsung.com>,
        <linux-fsd@tesla.com>, "'Bharat Uppal'" <bharat.uppal@samsung.com>
In-Reply-To: <20220531012220.80563-6-alim.akhtar@samsung.com>
Subject: RE: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci
Date:   Tue, 31 May 2022 16:37:11 +0900
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Hi,

> -----Original Message-----
> From: Alim Akhtar <alim.akhtar=40samsung.com>
> Sent: Tuesday, May 31, 2022 10:22 AM
> To: linux-arm-kernel=40lists.infradead.org; linux-kernel=40vger.kernel.or=
g;
> linux-scsi=40vger.kernel.org; linux-phy=40lists.infradead.org
> Cc: devicetree=40vger.kernel.org; robh+dt=40kernel.org;
> krzysztof.kozlowski+dt=40linaro.org; vkoul=40kernel.org; avri.altman=40wd=
c.com;
> bvanassche=40acm.org; martin.petersen=40oracle.com; chanho61.park=40samsu=
ng.com;
> pankaj.dubey=40samsung.com; Alim Akhtar <alim.akhtar=40samsung.com>; linu=
x-
> fsd=40tesla.com; Bharat Uppal <bharat.uppal=40samsung.com>
> Subject: =5BPATCH 5/6=5D ufs: host: ufs-exynos: add support for fsd ufs h=
ci
>=20
> Adds support of UFS HCI which is found in Tesla FSD SoC. FSD also have an
> addition bit for MPHY APB clock which was not there (was reserved) for
> previous exynos SoC.
>=20
> Cc: linux-fsd=40tesla.com
> Signed-off-by: Bharat Uppal <bharat.uppal=40samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar=40samsung.com>
> ---
>  drivers/ufs/host/ufs-exynos.c =7C 143 +++++++++++++++++++++++++++++++++-
>  1 file changed, 142 insertions(+), 1 deletion(-)
>=20
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.=
c
> index a81d8cbd542f..b3efdc4caca2 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> =40=40 -52,11 +52,12 =40=40
>  =23define HCI_ERR_EN_DME_LAYER	0x88
>  =23define HCI_CLKSTOP_CTRL	0xB0
>  =23define REFCLKOUT_STOP		BIT(4)
> +=23define MPHY_APBCLK_STOP        BIT(3)
>  =23define REFCLK_STOP		BIT(2)
>  =23define UNIPRO_MCLK_STOP	BIT(1)
>  =23define UNIPRO_PCLK_STOP	BIT(0)
>  =23define CLK_STOP_MASK		(REFCLKOUT_STOP =7C REFCLK_STOP =7C=5C
> -				 UNIPRO_MCLK_STOP =7C=5C
> +				 UNIPRO_MCLK_STOP =7C MPHY_APBCLK_STOP=7C=5C

Please make this change into a separate patch of this series.

>  				 UNIPRO_PCLK_STOP)
>  =23define HCI_MISC		0xB4
>  =23define REFCLK_CTRL_EN		BIT(7)
> =40=40 -386,6 +387,104 =40=40 static int exynos7_ufs_post_pwr_change(stru=
ct
> exynos_ufs *ufs,
>  	return 0;
>  =7D
>=20
> +static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs) =7B
> +	int i;
> +	struct ufs_hba *hba =3D ufs->hba;
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs-
> >mclk_rate);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> +	for_each_ufs_tx_lane(ufs, i) =7B
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L /
> ufs->mclk_rate);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
> +	=7D
> +
> +	for_each_ufs_rx_lane(ufs, i) =7B
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L /
> ufs->mclk_rate);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
> +	=7D
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0);

Use PA_LOCAL_TX_LCC_ENABLE instead of 0x155E. I think you can find more val=
ues from unipro.h.
Please try to use as much as possible :)

> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1);

They can be set from exynos_ufs_establish_connt.

> +
> +	return 0;
> +=7D
> +
> +static inline int fsd_ufs_post_link(struct exynos_ufs *ufs) =7B
> +	int i;
> +	struct ufs_hba *hba =3D ufs->hba;
> +	u32 hw_cap_min_tactivate;
> +	u32 peer_rx_min_actv_time_cap;
> +	u32 max_rx_hibern8_time_cap;
> +
> +	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
> +			&hw_cap_min_tactivate); /* HW Capability of
> MIN_TACTIVATE */
> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
> +			&peer_rx_min_actv_time_cap);    /* PA_TActivate */
> +	ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
> +			&max_rx_hibern8_time_cap);      /* PA_Hibern8Time */
> +
> +	if (peer_rx_min_actv_time_cap >=3D hw_cap_min_tactivate)
> +		ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
> +					peer_rx_min_actv_time_cap + 1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap +
> 1);
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> +	for_each_ufs_rx_lane(ufs, i) =7B
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
> +		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
> +	=7D
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +
> +	return 0;
> +=7D
> +
> +static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> +					struct ufs_pa_layer_attr *pwr)
> +=7B
> +	struct ufs_hba *hba =3D ufs->hba;
> +
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000);
> +	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000);
> +
> +	unipro_writel(ufs, 8064, 0x7888);
> +	unipro_writel(ufs, 28224, 0x788C);
> +	unipro_writel(ufs, 20160, 0x7890);
> +	unipro_writel(ufs, 12000, 0x78B8);
> +	unipro_writel(ufs, 32000, 0x78BC);
> +	unipro_writel(ufs, 16000, 0x78C0);
> +
> +	return 0;
> +=7D
> +
>  /*
>   * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
>   * Control should be disabled in the below cases =40=40 -1595,6 +1694,46=
 =40=40
> static struct exynos_ufs_drv_data exynos_ufs_drvs =3D =7B
>  	.post_pwr_change	=3D exynos7_ufs_post_pwr_change,
>  =7D;
>=20
> +static struct exynos_ufs_uic_attr fsd_uic_attr =3D =7B
> +	.tx_trailingclks		=3D 0x10,
> +	.tx_dif_p_nsec			=3D 3000000,	/* unit: ns */
> +	.tx_dif_n_nsec			=3D 1000000,	/* unit: ns */
> +	.tx_high_z_cnt_nsec		=3D 20000,	/* unit: ns */
> +	.tx_base_unit_nsec		=3D 100000,	/* unit: ns */
> +	.tx_gran_unit_nsec		=3D 4000,		/* unit: ns */
> +	.tx_sleep_cnt			=3D 1000,		/* unit: ns */
> +	.tx_min_activatetime		=3D 0xa,
> +	.rx_filler_enable		=3D 0x2,
> +	.rx_dif_p_nsec			=3D 1000000,	/* unit: ns */
> +	.rx_hibern8_wait_nsec		=3D 4000000,	/* unit: ns */
> +	.rx_base_unit_nsec		=3D 100000,	/* unit: ns */
> +	.rx_gran_unit_nsec		=3D 4000,		/* unit: ns */
> +	.rx_sleep_cnt			=3D 1280,		/* unit: ns */
> +	.rx_stall_cnt			=3D 320,		/* unit: ns */
> +	.rx_hs_g1_sync_len_cap		=3D SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g2_sync_len_cap		=3D SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g3_sync_len_cap		=3D SYNC_LEN_COARSE(0xf),
> +	.rx_hs_g1_prep_sync_len_cap	=3D PREP_LEN(0xf),
> +	.rx_hs_g2_prep_sync_len_cap	=3D PREP_LEN(0xf),
> +	.rx_hs_g3_prep_sync_len_cap	=3D PREP_LEN(0xf),
> +	.pa_dbg_option_suite		=3D 0x2E820183,
> +=7D;
> +
> +struct exynos_ufs_drv_data fsd_ufs_drvs =3D =7B
> +	.uic_attr               =3D &fsd_uic_attr,
> +	.quirks                 =3D UFSHCD_QUIRK_PRDT_BYTE_GRAN =7C
> +				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR =7C
> +				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR =7C
> +				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
> +	.opts                   =3D EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL =7C
> +				  EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL =7C
> +				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR =7C
> +				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
> +	.pre_link               =3D fsd_ufs_pre_link,
> +	.post_link              =3D fsd_ufs_post_link,
> +	.pre_pwr_change         =3D fsd_ufs_pre_pwr_change,
> +=7D;
> +
>  static const struct of_device_id exynos_ufs_of_match=5B=5D =3D =7B
>  	=7B .compatible =3D =22samsung,exynos7-ufs=22,
>  	  .data	      =3D &exynos_ufs_drvs =7D,
> =40=40 -1602,6 +1741,8 =40=40 static const struct of_device_id
> exynos_ufs_of_match=5B=5D =3D =7B
>  	  .data	      =3D &exynosauto_ufs_drvs =7D,
>  	=7B .compatible =3D =22samsung,exynosautov9-ufs-vh=22,
>  	  .data	      =3D &exynosauto_ufs_vh_drvs =7D,
> +	=7B .compatible =3D =22tesla,fsd-ufs=22,
> +	  .data       =3D &fsd_ufs_drvs =7D,
>  	=7B=7D,
>  =7D;
>=20
> --
> 2.25.1