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Date:   Wed, 01 Jun 2022 13:20:28 +0100
From:   "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To:     "Huacai Chen" <chenhuacai@loongson.cn>,
        "Arnd Bergmann" <arnd@arndb.de>,
        "Andy Lutomirski" <luto@kernel.org>,
        "Thomas Gleixner" <tglx@linutronix.de>,
        "Peter Zijlstra" <peterz@infradead.org>,
        "Andrew Morton" <akpm@linux-foundation.org>,
        "David Airlie" <airlied@linux.ie>,
        "Jonathan Corbet" <corbet@lwn.net>,
        "Linus Torvalds" <torvalds@linux-foundation.org>
Cc:     linux-arch@vger.kernel.org, linux-doc@vger.kernel.org,
        linux-kernel@vger.kernel.org, "Xuefeng Li" <lixuefeng@loongson.cn>,
        "Yanteng Si" <siyanteng@loongson.cn>,
        "Huacai Chen" <chenhuacai@gmail.com>,
        "Guo Ren" <guoren@kernel.org>, "Xuerui Wang" <kernel@xen0n.name>,
        "Stephen Rothwell" <sfr@canb.auug.org.au>,
        "Daniel Vetter" <daniel@ffwll.ch>, dri-devel@lists.freedesktop.org,
        "WANG Xuerui" <git@xen0n.name>
Subject: Re: [PATCH V12 06/24] LoongArch: Add writecombine support for drm
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=E5=9C=A82022=E5=B9=B46=E6=9C=881=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8A=E5=
=8D=8810:59=EF=BC=8CHuacai Chen=E5=86=99=E9=81=93=EF=BC=9A
> LoongArch maintains cache coherency in hardware, but its WUC attribute
> (Weak-ordered UnCached, which is similar to WC) is out of the scope of
> cache coherency machanism. This means WUC can only used for write-only
> memory regions.
>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: WANG Xuerui <git@xen0n.name>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Can still remember painful experiences on poke with WC on LS3B1500 + Pol=
aris.
Glad to see that WC is flawless this time.

Thanks.

> ---
>  drivers/gpu/drm/drm_vm.c         | 2 +-
>  drivers/gpu/drm/ttm/ttm_module.c | 2 +-
>  include/drm/drm_cache.h          | 8 ++++++++
>  3 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
> index e957d4851dc0..f024dc93939e 100644
> --- a/drivers/gpu/drm/drm_vm.c
> +++ b/drivers/gpu/drm/drm_vm.c
> @@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *ma=
p,
>  	pgprot_t tmp =3D vm_get_page_prot(vma->vm_flags);
>=20
>  #if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__)=20
> || \
> -    defined(__mips__)
> +    defined(__mips__) || defined(__loongarch__)
>  	if (map->type =3D=3D _DRM_REGISTERS && !(map->flags &=20
> _DRM_WRITE_COMBINING))
>  		tmp =3D pgprot_noncached(tmp);
>  	else
> diff --git a/drivers/gpu/drm/ttm/ttm_module.c=20
> b/drivers/gpu/drm/ttm/ttm_module.c
> index a3ad7c9736ec..b3fffe7b5062 100644
> --- a/drivers/gpu/drm/ttm/ttm_module.c
> +++ b/drivers/gpu/drm/ttm/ttm_module.c
> @@ -74,7 +74,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching=20
> caching, pgprot_t tmp)
>  #endif /* CONFIG_UML */
>  #endif /* __i386__ || __x86_64__ */
>  #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> -	defined(__powerpc__) || defined(__mips__)
> +	defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
>  	if (caching =3D=3D ttm_write_combined)
>  		tmp =3D pgprot_writecombine(tmp);
>  	else
> diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
> index 22deb216b59c..08e0e3ffad13 100644
> --- a/include/drm/drm_cache.h
> +++ b/include/drm/drm_cache.h
> @@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void)
>  	 * optimization entirely for ARM and arm64.
>  	 */
>  	return false;
> +#elif defined(CONFIG_LOONGARCH)
> +	/*
> +	 * LoongArch maintains cache coherency in hardware, but its WUC=20
> attribute
> +	 * (Weak-ordered UnCached, which is similar to WC) is out of the=20
> scope of
> +	 * cache coherency machanism. This means WUC can only used for=20
> write-only
> +	 * memory regions.
> +	 */
> +	return false;
>  #else
>  	return true;
>  #endif
> --=20
> 2.27.0

--=20
- Jiaxun