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Date:   Tue, 31 May 2022 12:50:30 +0100
From:   "Russell King (Oracle)" <linux@armlinux.org.uk>
To:     Siddharth Vadapalli <s-vadapalli@ti.com>
Cc:     davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
        pabeni@redhat.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, vladimir.oltean@nxp.com,
        grygorii.strashko@ti.com, vigneshr@ti.com, nsekhar@ti.com,
        netdev@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, kishon@ti.com
Subject: Re: [PATCH 2/3] net: ethernet: ti: am65-cpsw: Add support for QSGMII
 mode
Message-ID: <YpYBBp8Io116bBwM@shell.armlinux.org.uk>
References: <20220531113058.23708-1-s-vadapalli@ti.com>
 <20220531113058.23708-3-s-vadapalli@ti.com>
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Sender: Russell King (Oracle) <linux@armlinux.org.uk>
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On Tue, May 31, 2022 at 05:00:57PM +0530, Siddharth Vadapalli wrote:
>  static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode,
>  				      const struct phylink_link_state *state)
>  {
> -	/* Currently not used */
> +	struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
> +							  phylink_config);
> +	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
> +
> +	if (state->interface == PHY_INTERFACE_MODE_QSGMII)
> +		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
> +		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);

What about writing this register when the interface mode isn't QSGMII?

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