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[23.128.96.19]) by mx.google.com with ESMTPS id l6-20020a17090a150600b001e2c9663635si7674731pja.159.2022.06.01.13.13.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 13:13:43 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=hyQhii5o; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2BFAB170F3E; Wed, 1 Jun 2022 12:26:54 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237608AbiEaAhC (ORCPT + 99 others); Mon, 30 May 2022 20:37:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232584AbiEaAhA (ORCPT ); Mon, 30 May 2022 20:37:00 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97B56D126; Mon, 30 May 2022 17:36:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1653957418; x=1685493418; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=6upXiLhngd2diRhq3wzsffUdKH9r4qgqjL/Ge5fuhHI=; b=hyQhii5o4HLBCIpviOOYu+iH0l55QuoTlPuhrbh16CCVzLUe08l6negw 5WXXXdCklLQyTt31a6QjrKKhJqFNWVyPGkbsyQra1rbpRhKO8q07KGDkm 6SUW0/BTSvgcHkX9RCsoyPJGzaqdSfQ0K+zgRaqU7KRYtE6GMtff22Ix1 4=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 30 May 2022 17:36:57 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2022 17:36:57 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 30 May 2022 17:36:56 -0700 Received: from [10.38.244.253] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 30 May 2022 17:36:54 -0700 Message-ID: <68443e94-32fc-a35e-3383-0dcd8ca967c0@quicinc.com> Date: Mon, 30 May 2022 17:36:51 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH] drm/msm/dpu: Fix pointer dereferenced before checking Content-Language: en-US To: Haowen Bai , Rob Clark , "Dmitry Baryshkov" , Sean Paul , "David Airlie" , Daniel Vetter CC: , , , References: <1653896005-25168-1-git-send-email-baihaowen@meizu.com> From: Abhinav Kumar In-Reply-To: <1653896005-25168-1-git-send-email-baihaowen@meizu.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,RDNS_NONE,SPF_HELO_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/30/2022 12:33 AM, Haowen Bai wrote: > The ctx->hw is dereferencing before null checking, so move > it after checking. > > Signed-off-by: Haowen Bai Agree with Dmitry's comment. Adjust the patch subject to a different one otherwise PW thinks they are same patches. Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c > index bcccce292937..e59680cdd0ce 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c > @@ -155,11 +155,13 @@ static void dpu_hw_wb_roi(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *wb) > static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx, > struct dpu_hw_wb_qos_cfg *cfg) > { > - struct dpu_hw_blk_reg_map *c = &ctx->hw; > + struct dpu_hw_blk_reg_map *c; > u32 qos_ctrl = 0; > > if (!ctx || !cfg) > return; > + > + c = &ctx->hw; > > DPU_REG_WRITE(c, WB_DANGER_LUT, cfg->danger_lut); > DPU_REG_WRITE(c, WB_SAFE_LUT, cfg->safe_lut);