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From:   Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com>
To:     ulf.hansson@linaro.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, bhupesh.sharma@linaro.org
Cc:     linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, quic_rampraka@quicinc.com,
        quic_pragalla@quicinc.com, quic_sartgarg@quicinc.com,
        quic_nitirawa@quicinc.com, quic_sayalil@quicinc.com,
        Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com>
Subject: [PATCH V5] dt-bindings: mmc: sdhci-msm: Add gcc resets strings
Date:   Thu,  2 Jun 2022 17:14:51 +0530
Message-Id: <1654170291-29910-1-git-send-email-quic_c_sbhanu@quicinc.com>
Precedence: bulk

Add gcc hardware reset supported strings for qcom-sdhci controller

Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes since V4:
	- Updated Dt bindings changes YAML format as suggested by
	  Ulf Hansson.

Changes since V3:
	- Removed reset-names from DT bindings as suggested by
	  Stephen Boyd.
---
 Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index e423633..5548c35 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -121,6 +121,9 @@ properties:
     description: A phandle to sdhci power domain node
     maxItems: 1
 
+  resets:
+    description: Phandle and reset specifier for the device's reset.
+
 patternProperties:
   '^opp-table(-[a-z0-9]+)?$':
     if:
@@ -157,6 +160,8 @@ examples:
                    <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
       interrupt-names = "hc_irq", "pwr_irq";
 
+      resets = <&gcc GCC_SDCC2_BCR>;
+
       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
                <&gcc GCC_SDCC2_APPS_CLK>,
                <&rpmhcc RPMH_CXO_CLK>;
-- 
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