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From:   Bharat Kumar Gogada <bharatku@xilinx.com>
To:     Rob Herring <robh@kernel.org>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        Michal Simek <michals@xilinx.com>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: RE: [PATCH v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order
Thread-Topic: [PATCH v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order
Thread-Index: AQHYaQ7VIq93UpHHX0WumtBeKR0BEK07EPGAgAIoNNA=
Date:   Fri, 3 Jun 2022 04:52:18 +0000
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References: <20220516102217.25960-1-bharat.kumar.gogada@xilinx.com>
 <20220601195523.GA328031-robh@kernel.org>
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> Subject: Re: [PATCH v2] dt-bindings: PCI: xilinx-cpm: Fix reg property or=
der
>=20
> On Mon, 16 May 2022 15:52:17 +0530, Bharat Kumar Gogada wrote:
> > All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" re=
g.
> >
> > This order is also suggested by node name which is pcie@fca10000 which
> > suggests that cpm_slcr register should be the first.
> >
> > Driver itself is using devm_platform_ioremap_resource_byname() for
> > both names that's why there is no functional change even on
> > description which are using current order.
> >
> > But still prefer to change order to cover currently used description.
> > Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM
> > Root Port")
> >
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > ---
> >  .../devicetree/bindings/pci/xilinx-versal-cpm.yaml     | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
>=20
> Applied, thanks!

Thanks Rob.