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Fri, 3 Jun 2022 23:47:22 -0500 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 6/8] perf/x86/ibs: Add new IBS register bits into header Date: Sat, 4 Jun 2022 10:15:17 +0530 Message-ID: <20220604044519.594-7-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604044519.594-1-ravi.bangoria@amd.com> References: <20220604044519.594-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3fdbf4ab-6f1d-4fed-bd50-08da45e557a5 X-MS-TrafficTypeDiagnostic: IA1PR12MB6353:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sa23r3sjFNNtjgcOHhS7f+xkn85mtBkZOUr3CwMWct6VPBLkHvbpf4tfmNVWnGv5KGneMTN3Ev3ZtPrQWKN013yKuuozTNNURIChqJSPwcuoxJmQctTeF2ikt8P8fSa3yHq8U/U0QCzd0hXMaZ/IP0BfEfc2ZgLOXSC/L4k6tKmo+VJXbgVRJme43Kezi0REoAwnLMzfoO6HYE2D/UUvQp4IXa/+cUJyCBB0c1uxAqc+sPN/ORt0+rYIO4LH3SkFOLXOuLVNsbGNyVhHuwNOP5HBx7HVziOrLHsn2rkpXO0+ooxQ4pEEUZLL0eroA+vzroNe4wDkwUFgzB9+Kkclz468k+r3TJFvvwSaKwxJowSnsgxZbwK1dcBFczmVNIlHOUmPnvJc58LgY7VcxDmca6MJwLz7N2FhFDBcZAK0gfiKhpb6gPfO9gpko+rEz4mf6VD8OhpMkBRL6BjpI2lCEQ6MOk8AQK3HNW4d/POuX59dEhWtzXZNRTAlG6fQHapZwWrqtAOGx7HhfnrDf/aG08p8ZJPTdR5bv6ypGHWNyYgGDaFkN08QsAJJjUfzuFXnKmmc+lAbJtgUF7mjOxcT5paY4KbesxH7wvlRnMQa6uVUMjiJ9hw4s3D/qOU29xuxhH9vMazQ81fvjcLcQAOLh6zSPbDwGYNEWaLjFAp3InK2fqr9uwLIXSR1FHl508ypTtUGWmcJa7pHlyYs9C3TJQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(7696005)(26005)(5660300002)(2906002)(2616005)(16526019)(186003)(83380400001)(47076005)(82310400005)(7416002)(426003)(6666004)(336012)(8936002)(36756003)(1076003)(44832011)(4326008)(86362001)(8676002)(356005)(316002)(70206006)(70586007)(6916009)(54906003)(508600001)(81166007)(36860700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2022 04:47:34.6028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3fdbf4ab-6f1d-4fed-bd50-08da45e557a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6353 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org IBS support has been enhanced with two new features in upcoming uarch: 1. DataSrc extension and 2. L3 miss filtering. Additional set of bits has been introduced in IBS registers to exploit these features. Define these new bits into arch/x86/ header. Signed-off-by: Ravi Bangoria Acked-by: Ian Rogers --- arch/x86/include/asm/amd-ibs.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h index aabdbb5ab920..f3eb098d63d4 100644 --- a/arch/x86/include/asm/amd-ibs.h +++ b/arch/x86/include/asm/amd-ibs.h @@ -29,7 +29,10 @@ union ibs_fetch_ctl { rand_en:1, /* 57: random tagging enable */ fetch_l2_miss:1,/* 58: L2 miss for sampled fetch * (needs IbsFetchComp) */ - reserved:5; /* 59-63: reserved */ + l3_miss_only:1, /* 59: Collect L3 miss samples only */ + fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */ + fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */ + reserved:2; /* 62-63: reserved */ }; }; @@ -38,14 +41,14 @@ union ibs_op_ctl { __u64 val; struct { __u64 opmaxcnt:16, /* 0-15: periodic op max. count */ - reserved0:1, /* 16: reserved */ + l3_miss_only:1, /* 16: Collect L3 miss samples only */ op_en:1, /* 17: op sampling enable */ op_val:1, /* 18: op sample valid */ cnt_ctl:1, /* 19: periodic op counter control */ opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */ - reserved1:5, /* 27-31: reserved */ + reserved0:5, /* 27-31: reserved */ opcurcnt:27, /* 32-58: periodic op counter current count */ - reserved2:5; /* 59-63: reserved */ + reserved1:5; /* 59-63: reserved */ }; }; @@ -71,11 +74,12 @@ union ibs_op_data { union ibs_op_data2 { __u64 val; struct { - __u64 data_src:3, /* 0-2: data source */ + __u64 data_src_lo:3, /* 0-2: data source low */ reserved0:1, /* 3: reserved */ rmt_node:1, /* 4: destination node */ cache_hit_st:1, /* 5: cache hit state */ - reserved1:57; /* 5-63: reserved */ + data_src_hi:2, /* 6-7: data source high */ + reserved1:56; /* 8-63: reserved */ }; }; -- 2.31.1