Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19;
Feedback-ID: ifd894703:Fastmail
From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
To:     chenhuacai@kernel.org
Cc:     kernel@xen0n.name, maz@kernel.org, linux-kernel@vger.kernel.org,
        linux-mips@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH for-5.19 2/2] loongarch: Mask out higher bits for get_csr_cpuid
Date:   Sat,  4 Jun 2022 13:40:52 +0100
Message-Id: <20220604124052.1550-2-jiaxun.yang@flygoat.com>
In-Reply-To: <20220604124052.1550-1-jiaxun.yang@flygoat.com>
References: <20220604124052.1550-1-jiaxun.yang@flygoat.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Only low 9 bits of CPUID CSR represents coreid, higher bits
are marked as reserved. In case Loongson may define higher
bits in future, just mask them out for get_csr_cpuid.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/loongarch/include/asm/loongarch.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 3ba4f7e87cd2..7f3933f747f9 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1200,7 +1200,7 @@ static inline u64 drdtime(void)
 
 static inline unsigned int get_csr_cpuid(void)
 {
-	return csr_read32(LOONGARCH_CSR_CPUID);
+	return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
 }
 
 static inline void csr_any_send(unsigned int addr, unsigned int data,
-- 
2.25.1