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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id fh22-20020a17090b035600b001dc3a299f5bsi24073364pjb.114.2022.06.06.09.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 09:38:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 54B2529A62B; Mon, 6 Jun 2022 09:20:44 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241678AbiFFQUb (ORCPT + 99 others); Mon, 6 Jun 2022 12:20:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241663AbiFFQT7 (ORCPT ); Mon, 6 Jun 2022 12:19:59 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EFD2924AC86; Mon, 6 Jun 2022 09:19:57 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF11E1595; Mon, 6 Jun 2022 09:19:57 -0700 (PDT) Received: from FVFF77S0Q05N.cambridge.arm.com (FVFF77S0Q05N.cambridge.arm.com [10.1.37.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 79FB63F73B; Mon, 6 Jun 2022 09:19:54 -0700 (PDT) Date: Mon, 6 Jun 2022 17:19:42 +0100 From: Mark Rutland To: Alexander Lobakin Cc: Arnd Bergmann , Yury Norov , Andy Shevchenko , Richard Henderson , Matt Turner , Brian Cain , Geert Uytterhoeven , Yoshinori Sato , Rich Felker , "David S. Miller" , Kees Cook , "Peter Zijlstra (Intel)" , Marco Elver , Borislav Petkov , Tony Luck , Greg Kroah-Hartman , linux-alpha@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/6] bitops: define gen_test_bit() the same way as the rest of functions Message-ID: References: <20220606114908.962562-1-alexandr.lobakin@intel.com> <20220606114908.962562-4-alexandr.lobakin@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220606114908.962562-4-alexandr.lobakin@intel.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RDNS_NONE, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 06, 2022 at 01:49:04PM +0200, Alexander Lobakin wrote: > Currently, the generic test_bit() function is defined as a one-liner > and in case with constant bitmaps the compiler is unable to optimize > it to a constant. At the same time, gen_test_and_*_bit() are being > optimized pretty good. > Define gen_test_bit() the same way as they are defined. > > Signed-off-by: Alexander Lobakin Regardless of whether compilers prefer this, I think it's nicer to have the structure consistent with the rest of the functions, so FWIW: Acked-by: Mark Rutland Mark. > --- > include/asm-generic/bitops/generic-non-atomic.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/include/asm-generic/bitops/generic-non-atomic.h b/include/asm-generic/bitops/generic-non-atomic.h > index 7a60adfa6e7d..202d8a3b40e1 100644 > --- a/include/asm-generic/bitops/generic-non-atomic.h > +++ b/include/asm-generic/bitops/generic-non-atomic.h > @@ -118,7 +118,11 @@ gen___test_and_change_bit(unsigned int nr, volatile unsigned long *addr) > static __always_inline int > gen_test_bit(unsigned int nr, const volatile unsigned long *addr) > { > - return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); > + const unsigned long *p = (const unsigned long *)addr + BIT_WORD(nr); > + unsigned long mask = BIT_MASK(nr); > + unsigned long val = *p; > + > + return !!(val & mask); > } > > #endif /* __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H */ > -- > 2.36.1 >