Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Ankur Arora <ankur.a.arora@oracle.com>
To:     linux-kernel@vger.kernel.org, linux-mm@kvack.org, x86@kernel.org
Cc:     torvalds@linux-foundation.org, akpm@linux-foundation.org,
        mike.kravetz@oracle.com, mingo@kernel.org, luto@kernel.org,
        tglx@linutronix.de, bp@alien8.de, peterz@infradead.org,
        ak@linux.intel.com, arnd@arndb.de, jgg@nvidia.com,
        jon.grimm@amd.com, boris.ostrovsky@oracle.com,
        konrad.wilk@oracle.com, joao.m.martins@oracle.com,
        ankur.a.arora@oracle.com
Subject: [PATCH v3 16/21] x86/clear_page: add arch_clear_page_non_caching_threshold()
Date:   Mon,  6 Jun 2022 20:37:20 +0000
Message-Id: <20220606203725.1313715-12-ankur.a.arora@oracle.com>
In-Reply-To: <20220606202109.1306034-1-ankur.a.arora@oracle.com>
References: <20220606202109.1306034-1-ankur.a.arora@oracle.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?REJDy9VIA8kxa1DNULchMa/g+t59pHpLwzy62XpvUNZEDp+GJvY9Qql5e9CF?=
 =?us-ascii?Q?0kiwh5fXyg8QE0pi4nFxzrygi4xY/QJEagyePlsmIfcSM6wwR5h6KTQZLuEK?=
 =?us-ascii?Q?xyjymsTOHIw+7e/+xhwqnRolT5E6Iakp55YOklVQT4BhQPqycC/F6SchcKEv?=
 =?us-ascii?Q?KFDpy4H3gmjGuaxEHyLwhMozF9XK2qrp6kymWKqAkbuK4Hw+72VkouX06wzS?=
 =?us-ascii?Q?qro0g42ZuzLeAcIH4+ypB16IU4FTuDybsM9h+BCGrHv5akyi6Zab756Dv7Oc?=
 =?us-ascii?Q?/wn7f4eo9usSYgAgpyi4wJk5ydZSjY6tygiflZ4an0s32qv3cTVU6uPy4nc9?=
 =?us-ascii?Q?rSzZhGPvhtUzUH2Myzev7AzTEdl7wleQmV5AFOUFNWVeQlMSYR69ERashcV/?=
 =?us-ascii?Q?9l7utmq/7GQjesrBT4vu8+HqINlEl6WmkYU0VjSkn+jJ8z7bZyVOT19NAoew?=
 =?us-ascii?Q?6Rv/FJ+QKpgZwAAuR8io5xjuTvkjuVelpuGkeWZahWTikc1lFTV0XwwJ7gQb?=
 =?us-ascii?Q?0LtyYm3fT0paN1ZdKYzXdPiHu7UPMdq8ZvABPx2vGgUODC3oDhR807ZkmQC8?=
 =?us-ascii?Q?q4AFYMcE4nXITMLHArZ3Y3tnFPz8tux1hrT3u8BBfnPwPObww1BJUGb5aFB8?=
 =?us-ascii?Q?fYl+wvjVCzxAani6/4cuwm+wsrgZI1gSZfsDprcMfa4bRl3bvEkZ5Z5CsLI5?=
 =?us-ascii?Q?2tdS+oNavrKPxEjwMq5M2MU9LZJopRYeBRs+1O1jhJvNOhyAkLK6ZAMGobTn?=
 =?us-ascii?Q?ZOfqkEDGiM+qgH89b9rLVsIuVherzHOvtcmp7U1xwwtL80iQha9eW14N/TGG?=
 =?us-ascii?Q?nay+Izsz4RIIXckH+LsR+bP8PxBX7u5ZJFm5MLh9F43kGWTf1WJrlT/ERJof?=
 =?us-ascii?Q?v8whyjrsBjHHQqFdsp5ueJ5ND9d8zG2CHea8K635InMWowi/LTtPfXZSajaw?=
 =?us-ascii?Q?KYaEEtsRe59XfMVzu5fYfK26r5WS/UcqFPhvJSCRWyDCBmfVpAfNg1jwUwyG?=
 =?us-ascii?Q?ftaQuCKcpcYs51KskWx2nP9xpVJZFYbfkCDjrqxIq+GLf4vgiXBPkaLUcyGX?=
 =?us-ascii?Q?L73SbxTd5KSgfdrR3ebE3EFiWYkzWGxqGkb5KivmiygctJbrOeN22kp0f2Ce?=
 =?us-ascii?Q?bat/GOdzza/OqGPxtPFHF1w+2fruDLQU7JSuv3S61xgkTZ1qRKzixlUjm5xo?=
 =?us-ascii?Q?7w5pMVlQpiuhSh8+8aw+vOnIEh+LNslu4R4ve7me89jWgNDAZ+e7T3N2UFH7?=
 =?us-ascii?Q?QX/bX0KrQg0N16GiXw1KZUMoO1H8Kfl1jWUIDLSPYezO4uZftUssfjJvEhFP?=
 =?us-ascii?Q?+w0x5S5eDQCyHqW5Neqs8XcUsAil/z5hyrHE0qZXGTvlWIRQkAynqAAJWB/Y?=
 =?us-ascii?Q?V/tX4dkq3u9OdTDMnuxfOw36zQR1N18GvhU7GDTOaIaMCOjSuDgZL95RoYBa?=
 =?us-ascii?Q?+yLBfRK0Ih8rmF9YDiqb4ltYLYeRi+u0N3UTcr3+H4FaPnfqa6spTjIdB3CH?=
 =?us-ascii?Q?YWNm0ZzRrxVqFNTld0PbEqwCcPDPL3MgKotCUfm0/dpkluKb6eJmOoIFxXUT?=
 =?us-ascii?Q?nWhGzbcUvAjQxFu08yKGvD+oecClcQmLOa+cFnmrFwFXf2S8yh8/7lk9Sl+l?=
 =?us-ascii?Q?Ro3/HCVYRIA8fkPAssj6GzXsq5VWoCp3CvD87SBhRPCSRcj6nx2XEyjmgKzj?=
 =?us-ascii?Q?WkTiMAm8ABuqAe+jh/4nFeUo468MW5wFBjuCvBfYHI4AHRfrbUEFhydfgiq3?=
 =?us-ascii?Q?47kGNULE75cAbn/HSiveqOz86j+7jbY=3D?=
X-OriginatorOrg: oracle.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 11f4a2ea-7de7-4799-5f4b-08da47fc8d07
X-MS-Exchange-CrossTenant-AuthSource: DM8PR10MB5416.namprd10.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 20:38:45.0841
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: t7oe/4j3G9Jq1oDjdG2ks1SYekl4AZxr3KP5aFBtiCeFK2vjLBQ8Ysejy7WcUjK8fmsfkx5Gb418FaPB+sjYYQdpH5lc9nagIYVu2JGWrFo=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR10MB2734
X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.517,18.0.874
 definitions=2022-06-06_06:2022-06-02,2022-06-06 signatures=0
X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 mlxlogscore=999
 adultscore=0 bulkscore=0 mlxscore=0 suspectscore=0 malwarescore=0
 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1
 engine=8.12.0-2204290000 definitions=main-2206060081
X-Proofpoint-ORIG-GUID: bFyncl2rKsmgwuWKnXmiTtNg13Gu6Q1D
X-Proofpoint-GUID: bFyncl2rKsmgwuWKnXmiTtNg13Gu6Q1D
X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,
        RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE
        autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Add arch_clear_page_non_caching_threshold() for a machine specific value
above which clear_page_incoherent() would be used.

The ideal threshold value depends on the CPU model and where the
performance curves for caching and non-caching stores intersect.
A safe value is LLC-size, so we use that of the boot_cpu.

Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
---
 arch/x86/include/asm/cacheinfo.h |  1 +
 arch/x86/kernel/cpu/cacheinfo.c  | 13 +++++++++++++
 arch/x86/kernel/setup.c          |  6 ++++++
 3 files changed, 20 insertions(+)

diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cacheinfo.h
index 86b2e0dcc4bf..5c6045699e94 100644
--- a/arch/x86/include/asm/cacheinfo.h
+++ b/arch/x86/include/asm/cacheinfo.h
@@ -4,5 +4,6 @@
 
 void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu);
 void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu);
+int cacheinfo_lookup_max_size(int cpu);
 
 #endif /* _ASM_X86_CACHEINFO_H */
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index fe98a1465be6..6fb0cb868099 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -1034,3 +1034,16 @@ int populate_cache_leaves(unsigned int cpu)
 
 	return 0;
 }
+
+int cacheinfo_lookup_max_size(int cpu)
+{
+	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+	struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+	struct cacheinfo *max_leaf;
+
+	/*
+	 * Assume that cache sizes always increase with level.
+	 */
+	max_leaf = this_leaf + this_cpu_ci->num_leaves - 1;
+	return max_leaf->size;
+}
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 249981bf3d8a..701825a22863 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -50,6 +50,7 @@
 #include <asm/thermal.h>
 #include <asm/unwind.h>
 #include <asm/vsyscall.h>
+#include <asm/cacheinfo.h>
 #include <linux/vmalloc.h>
 
 /*
@@ -1293,3 +1294,8 @@ static int __init register_kernel_offset_dumper(void)
 	return 0;
 }
 __initcall(register_kernel_offset_dumper);
+
+unsigned long __init arch_clear_page_non_caching_threshold(void)
+{
+	return cacheinfo_lookup_max_size(0);
+}
-- 
2.31.1