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[80.7.220.175]) by smtp.gmail.com with ESMTPSA id j37-20020a05600c1c2500b0039c3056c3dfsm1727181wms.27.2022.06.07.01.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 01:47:50 -0700 (PDT) Date: Tue, 7 Jun 2022 09:47:48 +0100 From: Daniel Thompson To: richard clark Cc: Marc Zyngier , Robin Murphy , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, s32@nxp.com, leoyang.li@nxp.com, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com Subject: Re: Question about SPIs' interrupt trigger type restrictions Message-ID: <20220607084748.45bc7qzxjjinb7mm@maple.lan> References: <35f95ba3-8a7b-7918-0f9d-e14274a5ffe9@arm.com> <87ee0gn5rq.wl-maz@kernel.org> <20220530084039.7rjjbm4gkplg5747@maple.lan> <20220606100848.ir4bkj5qsskxe6in@maple.lan> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 07, 2022 at 09:29:06AM +0800, richard clark wrote: > On Mon, Jun 6, 2022 at 6:08 PM Daniel Thompson > wrote: > > There is a secondary interrupt > > controller between the SoC pin and the GIC which inverts the logic (and > > also obviates any need to deploy the GIC's edge detection features at > > all... IMHO the GIC trigger mode should be active high). > > I don't think there's a interrupt controller between SOC WKPU and GIC, > all the WKPU interrupt related does is to *detect* the external > signal(falling/rising) and route to the GIC See below. > > Instead, I think the reason your code is weird is because the irqchip > > driver for the WKPU is missing or broken. A secondary interrupt > > controller requires an irqchip driver or you will end up with pieces of > > the interrupt controller management code (e.g. weird pokes to the WKPU > > to acknowledge things) appearing in all manner of inappropriate places. > > Again, no so-called second irq-chip except the GIC within the SOC. Yes there is. The WKPU is an interrupt controller and it sits between the SoC pin and the GIC. To avoid weird code then you need a WKPU driver. Drivers for interrupt controllers normally belong in drivers/irqchip. I believe, in your case, this driver is either missing or broken. This belief is based on evidence that you provided. You code appears to attach an ISR directly to a GIC SPI irqno: if an irqchip driver for the WKPU was present and working then I think you would be unable to do this (because it would be busy). > For me, the most important thing is WHY the GIC only support the > rising edge just as its document said. I can't help you with that. Sure, it might be interesting to know more but I'm a pragmatist: I simply not that invested in revisiting a fifteen year old design decision that can no longer be changed. Daniel.