Received: by 2002:a5d:9c59:0:0:0:0:0 with SMTP id 25csp2223238iof; Tue, 7 Jun 2022 23:42:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJypz1AxnDEHrvT2r+XgBJaVJX9s/Z9EPsKYuID75G/ATCIHMedlVHsmloqqkOH6AIdArhhA X-Received: by 2002:a17:90a:8d83:b0:1e3:3211:1cbd with SMTP id d3-20020a17090a8d8300b001e332111cbdmr46118111pjo.219.1654670540263; Tue, 07 Jun 2022 23:42:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654670540; cv=none; d=google.com; s=arc-20160816; b=ejqCJIVwMVRjrnIZ91LI3SSCSfeMT5wY93b2vaakRTDbs/TB9iFVdRzsgv+12028Gm 3IC6cC6WijibZKC/TXiM1Neqds6U/sDDWmKZMI55YSDSoKDChjpIZ/kisvog7ihqt7oU px5YrE0iQRkcoBMPKhP8OHBDOxiZjFldiQPSIY62toVukpYGllyqbjc/bbLOpBQxwLGO Zgv5CxOr7ysrW6hpCsWoBW7PfvLF8RPzsAPqzbpklOTxnXtlmR+IwrNMmkhxWY7twu7+ EPhUIyK35togdB97m/H80hV1OkI28FuDQLGKDQYaClGJzQas3pe57fKziJlYBfNR4Lrw YU+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:user-agent:references:message-id :in-reply-to:subject:cc:to:from:date:dkim-signature; bh=ET69IivRGPcjohq7IHlYXAxFq39Wjl2RtBkICsW/Fg0=; b=Eou//vx9nlK/nEP+ci+a/Ef+oZJps6XUqQZ3EayVE6F8FtTDH0+E2h3YNehebAFINT MetyI4iIO2Vr7BUXzfIyqNSVaA6oEh2H2PPwuPmQtj6RCo6jR+VBumHTwi3Jm1jm1kxp S/jtV5PWnoWCbDyM6RDYa1/lystYGftoO6BxhLA00OZaaSUAxn/nLjkDRodd0R18m6wf lDBlK8UkCTbgStYR7yZk6bB5laO4yAj4A6g3rtnLJMZEc7dUXPNX1D3cGzQrQYWKxSXu N15k2cC9q98SSHVqJZgyfVFTcsvsJMAwf2vfFfGyGfh5Bq+gNEG46zPucU3lPMlmrhtD k3Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=hlqoD294; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net. [2620:137:e000::1:18]) by mx.google.com with ESMTPS id u12-20020a63790c000000b003fab4d7f31asi27395952pgc.72.2022.06.07.23.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 23:42:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=hlqoD294; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AA8241900DA; Tue, 7 Jun 2022 23:02:28 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232208AbiFHDGI (ORCPT + 99 others); Tue, 7 Jun 2022 23:06:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376557AbiFHDCV (ORCPT ); Tue, 7 Jun 2022 23:02:21 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD29C1F5C40 for ; Tue, 7 Jun 2022 17:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654648250; x=1686184250; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=CAEs+eNkcEk5PucMiRuUH9VvF5OOvLGOLrW/nucQ0t0=; b=hlqoD294Eet11KRqzeOH3CsXk5uBGMkIHyKxuuv3Fie31r6/Co04ZZST AzJQYuqyVFXsmi5nPepu+wWvUO15d/eND0gtEhgRWCQeAv842LOfgrAZ3 tNNKEMD0M7lRDsTg+GSVguPCXPEgPIm6YNfeyrN3BPeSXZRmQi1u90W9a zFbivoYMFqaKa+dNSNsQDGrJv+ia7N/ZkJd6ZTDvhRV6q0e6cLRhQ/GED +rkZ2orxY/gX9qEabWjU8++mzfFYey+EQEt1c18burp6l9tGeSYOz4wsf v8v8NXYhkno7yqs6Tyo1v0JaLXMa4QvrEOb86d1Tz7z8Nt3YNqRgFPmut w==; X-IronPort-AV: E=McAfee;i="6400,9594,10371"; a="257206797" X-IronPort-AV: E=Sophos;i="5.91,284,1647327600"; d="scan'208";a="257206797" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2022 17:27:46 -0700 X-IronPort-AV: E=Sophos;i="5.91,284,1647327600"; d="scan'208";a="532864405" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2022 17:27:46 -0700 Date: Tue, 7 Jun 2022 17:27:38 -0700 (PDT) From: matthew.gerlach@linux.intel.com X-X-Sender: mgerlach@rhweight-WRK1 To: Mark Brown cc: Tianfei Zhang , gregkh@linuxfoundation.org, rafael@kernel.org, linux-kernel@vger.kernel.org, hao.wu@intel.com, trix@redhat.com, yilun.xu@intel.com, russell.h.weight@intel.com Subject: Re: [PATCH v1] regmap: add generic indirect regmap support In-Reply-To: Message-ID: References: <20220607013755.594554-1-tianfei.zhang@intel.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 7 Jun 2022, Mark Brown wrote: > On Mon, Jun 06, 2022 at 09:37:55PM -0400, Tianfei Zhang wrote: >> From: Matthew Gerlach >> >> This patch adds support for regmap APIs that are intended to be used by >> the drivers of some devices which support generic indirect register access, >> for example PMCI (Platform Management Control Interface) device, HSSI >> (High Speed Serial Interface) device in FPGA. > > What is "generic indirect register access"? I'm not clear what this is > intended to support... "indirect register access" is a RTL design pattern we use in FPGAs frequently. The design pattern involves a small number of registers plus a little handshake code to access various register spaces inside the FPGA fabric. The design pattern is "generic" in the sense that the same small number of registers and handshake can be used with many different IP components in the FPGA. Historically, the bit definitions and handshaking was slightly different for each IP component. This is an attempt at a consistent usage across IP components. Would a different name help? > >> +static int indirect_bus_clr_cmd(struct indirect_ctx *ctx) >> +{ >> + unsigned int cmd; >> + int ret; >> + >> + writel(0, ctx->base + INDIRECT_CMD_OFF); >> + ret = readl_poll_timeout((ctx->base + INDIRECT_CMD_OFF), cmd, >> + (!cmd), INDIRECT_INT_US, INDIRECT_TIMEOUT_US); >> + if (ret) >> + dev_err(ctx->dev, "%s timed out on clearing cmd 0x%xn", __func__, cmd); > > ...and this doesn't look particularly generic, it looks like it's for > some particular controller/bridge? >