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Date:   Wed, 08 Jun 2022 07:05:51 +0100
Message-ID: <87pmjjzo3k.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc:     Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Chao-ying Fu <cfu@wavecomp.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Geert Uytterhoeven <geert@linux-m68k.org>,
        Greg Ungerer <gerg@kernel.org>,
        Hauke Mehrtens <hauke@hauke-m.de>,
        Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
        linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
        Paul Burton <paulburton@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Serge Semin <fancer.lancer@gmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Tiezhu Yang <yangtiezhu@loongson.cn>
Subject: Re: [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support
In-Reply-To: <0a5dd632-0607-dab6-4de7-1ea248490863@flygoat.com>
References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com>
        <20220525121030.16054-7-Dragan.Mladjenovic@syrmia.com>
        <87wndu3tff.wl-maz@kernel.org>
        <0a5dd632-0607-dab6-4de7-1ea248490863@flygoat.com>
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On Tue, 07 Jun 2022 19:23:02 +0100,
Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>=20
>=20
>=20
> =E5=9C=A8 2022/6/6 12:47, Marc Zyngier =E5=86=99=E9=81=93:
> > On Wed, 25 May 2022 13:10:24 +0100,
> > Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com> wrote:
> >> From: Paul Burton <paulburton@kernel.org>
> >>=20
> >> The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept =
of
> >> multiple clusters to the system. In these systems each cluster contains
> >> its own GIC, so the GIC isn't truly global any longer. We do have the
> >> ability to access registers in the GICs of remote clusters using a
> >> redirect register block much like the redirect register blocks provided
> >> by the CM & CPC, and configured through the same GCR_REDIRECT register
> >> that we our mips_cm_lock_other() abstraction builds upon.
> >>=20
> >> It is expected that external interrupts are connected identically to a=
ll
> >> clusters. That is, if we have a device providing an interrupt connected
> >> to GIC interrupt pin 0 then it should be connected to pin 0 of every G=
IC
> >> in the system. This simplifies things somewhat by allowing us for the
> >> most part to treat the GIC as though it is still truly global, so long
> >> as we take care to configure interrupts in the cluster that we want th=
em
> >> affine to.
> > I can see how this can work for level interrupts, but how does this
> > work for edge interrupts? Is there any guarantee that the interrupt
> > will be discarded if routed to a cluster where it isn't configured?
> It is supposed to mask the interrupt out on the GIC which belongs to the
> cluster that the interrupt is not routed to.
>=20
> When it's masked out GIC simply won't sense any level change.
>=20
> I guess it's sort of guarantee?

Pretty much the opposite. There is a *strong* requirement that a
masked interrupt can still detect interrupts, so that on unmask the
interrupt fires (you'd otherwise lose edge interrupts pretty often).

What does the MIPS GIC arch spec says about this?

Thanks,

	M.

--=20
Without deviation from the norm, progress is not possible.