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[23.128.96.19]) by mx.google.com with ESMTPS id oa4-20020a17090b1bc400b001d9752b43absi29902290pjb.137.2022.06.08.04.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 04:21:08 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="kgFD/7uS"; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BCDDF12F355; Wed, 8 Jun 2022 03:43:48 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236935AbiFHKnX (ORCPT + 99 others); Wed, 8 Jun 2022 06:43:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236885AbiFHKnT (ORCPT ); Wed, 8 Jun 2022 06:43:19 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15535369E1 for ; Wed, 8 Jun 2022 03:43:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A78126120C for ; Wed, 8 Jun 2022 10:43:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 293DDC34116; Wed, 8 Jun 2022 10:43:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654684997; bh=0rzpE6UgFWk2qUmyC2Xz5lOzVZ7EhCvecB/fSMM6oe8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=kgFD/7uSPpv6sEfkIXw3IdjRStWpu8k8qWVJp0afiNrgFIT4+TGmVDKUg+1PFLDdZ JOm775EVux8mqs8DITKD8O3Nk06k8vCHcbQ+iaNdzrsTGUtmt8gJzuQKVZNtUsbe8N 7JvpFCUgPtENzrYyVMOQzROj+asVnP5axnSfevIt7JQZsGHrflLGzyswv12Kz3c67P FjIqzWgJKcEvBqi4YEJLIrpUWj4WofcgVxagBRx/b7TfutQMC+2YiCub5agQ5h0BnA XmpogfLbU5wHgR6TxKA8l8y2ZVBBIZoT8FZ3uB9Vy0SMxKgIKZlI12MJOH9aDiW6Kf xqPogR2rKfv3Q== Date: Wed, 8 Jun 2022 11:43:07 +0100 From: Mark Brown To: matthew.gerlach@linux.intel.com Cc: Tianfei Zhang , gregkh@linuxfoundation.org, rafael@kernel.org, linux-kernel@vger.kernel.org, hao.wu@intel.com, trix@redhat.com, yilun.xu@intel.com, russell.h.weight@intel.com Subject: Re: [PATCH v1] regmap: add generic indirect regmap support Message-ID: References: <20220607013755.594554-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="AJRKzDE6zVy7LGPR" Content-Disposition: inline In-Reply-To: X-Cookie: My NOSE is NUMB! X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --AJRKzDE6zVy7LGPR Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jun 07, 2022 at 05:27:38PM -0700, matthew.gerlach@linux.intel.com wrote: > On Tue, 7 Jun 2022, Mark Brown wrote: > > On Mon, Jun 06, 2022 at 09:37:55PM -0400, Tianfei Zhang wrote: > > > From: Matthew Gerlach > > > This patch adds support for regmap APIs that are intended to be used by > > > the drivers of some devices which support generic indirect register access, > > > for example PMCI (Platform Management Control Interface) device, HSSI > > > (High Speed Serial Interface) device in FPGA. > > What is "generic indirect register access"? I'm not clear what this is > > intended to support... > "indirect register access" is a RTL design pattern we use in FPGAs > frequently. The design pattern involves a small number of registers plus a > little handshake code to access various register spaces inside the FPGA > fabric. The design pattern is "generic" in the sense that the same small > number of registers and handshake can be used with many different IP > components in the FPGA. Historically, the bit definitions and handshaking > was slightly different for each IP component. This is an attempt at a > consistent usage across IP components. > Would a different name help? This wouldn't address the major problem which is... > > > + writel(0, ctx->base + INDIRECT_CMD_OFF); > > > + ret = readl_poll_timeout((ctx->base + INDIRECT_CMD_OFF), cmd, > > > + (!cmd), INDIRECT_INT_US, INDIRECT_TIMEOUT_US); > > > + if (ret) > > > + dev_err(ctx->dev, "%s timed out on clearing cmd 0x%xn", __func__, cmd); > > ...and this doesn't look particularly generic, it looks like it's for > > some particular controller/bridge? ...that this appears to be entirely specific to some particular device, it's got things like hard coded register addresses and timeouts which mean it can't be reused. --AJRKzDE6zVy7LGPR Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmKgfToACgkQJNaLcl1U h9CakQf/ZN6Q6QkrEb4nyhW8VMwyjRszU8l1d61t3KPA3ykEw9ycCVGWTcRpH11y /0nIkHr9dw8AB7/KJ78rYiqzzwjOndZb0ITjVY9Z9B4VC21RrcTttPeohl2MCoNM vFqQBh4dtbI4a9bOr3Wffz1bF+o/eB2CdkxMgelWlGPA3EXz8gZkPvLNM/FRcKM/ 4FLlszKfjHctNKepyEaxI05+Sgj3IxKEhhDXlWBG7jXz5J0lhHn/k+kuD/7PZR10 C3g/NHTJgHUH9RaBddZxRdzgVSH40ROucf77eHGMBVRpEB4+yEQclwB7bxorktLw Ql1heufgVlrMAkvp0UtSRm1X4Id98g== =zJWH -----END PGP SIGNATURE----- --AJRKzDE6zVy7LGPR--