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Date:   Wed, 8 Jun 2022 17:41:07 +0300
From:   Nikita Shubin <nikita.shubin@maquefel.me>
To:     John Garry <john.garry@huawei.com>
Cc:     Genevieve Chan <genevieve.chan@starfivetech.com>,
        =?UTF-8?B?Sm/Do28g?= =?UTF-8?B?TcOhcmlv?= Domingos 
        <joao.mario@tecnico.ulisboa.pt>,
        Nikita Shubin <n.shubin@yadro.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@kernel.org>,
        "Namhyung Kim" <namhyung@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        "Palmer Dabbelt" <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        <linux-kernel@vger.kernel.org>, <linux-perf-users@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>,
        Atish Patra <atishp@atishpatra.org>
Subject: Re: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile
Message-ID: <20220608174107.7b94e545@redslave.neermore.group>
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References: <20220607131648.29439-1-nikita.shubin@maquefel.me>
        <20220607131648.29439-4-nikita.shubin@maquefel.me>
        <9e981523-6032-fd24-08f9-0ef771cd1c2e@huawei.com>
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Hello, John.

On Wed, 8 Jun 2022 11:45:53 +0100
John Garry <john.garry@huawei.com> wrote:

> On 07/06/2022 14:16, Nikita Shubin wrote:
> > From: Jo=C3=A3o M=C3=A1rio Domingos <joao.mario@tecnico.ulisboa.pt>
> >=20
> > The pmu-events now supports custom events for RISC-V, plus the
> > cycle, time and instret events were defined.
> >=20
> > Signed-off-by: Jo=C3=A3o M=C3=A1rio Domingos <joao.mario@tecnico.ulisbo=
a.pt>
> > Tested-by: Nikita Shubin <n.shubin@yadro.com>
> > ---
> >   tools/perf/pmu-events/arch/riscv/mapfile.csv  | 14 +++++++++++++
> >   .../pmu-events/arch/riscv/riscv-generic.json  | 20
> > +++++++++++++++++++ 2 files changed, 34 insertions(+)
> >   create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> >   create mode 100644
> > tools/perf/pmu-events/arch/riscv/riscv-generic.json
> >=20
> > diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> > b/tools/perf/pmu-events/arch/riscv/mapfile.csv new file mode 100644
> > index 000000000000..4f2aa199d9cb
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> > @@ -0,0 +1,14 @@
> > +# Format:
> > +#	MIDR,Version,JSON/file/pathname,Type
> > +#
> > +# where
> > +#	MIDR	Processor version =20
>=20
> ARM, no?

I've messed with --cc-cmd badly and didn't include every one in cover
letter, sorry for that, attaching link to cover letter:

https://lore.kernel.org/all/20220607131648.29439-1-nikita.shubin@maquefel.m=
e/

They are ARM inspired indeed.


>=20
> > +#		Variant[23:20] and Revision [3:0] should be zero.
> > +#	Version could be used to track version of JSON file
> > +#		but currently unused.
> > +#	JSON/file/pathname is the path to JSON file, relative
> > +#		to tools/perf/pmu-events/arch/riscv/.
> > +#	Type is core, uncore etc
> > +#
> > +#
> > +#Family-model,Version,Filename,EventType
> > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json
> > b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode
> > 100644 index 000000000000..013e50efad99
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json =20
>=20
> where or how are these referenced?

Currently they are not referenced in this version of series at all,
their purpose is to be used like "ArchStdEvent".

Through any RISCV implementation should have at least these 3 events.

Yours,
Nikita Shubin.

>=20
> > @@ -0,0 +1,20 @@
> > +[
> > +  {
> > +    "PublicDescription": "CPU Cycles",
> > +    "EventCode": "0x00",
> > +    "EventName": "riscv_cycles",
> > +    "BriefDescription": "CPU cycles RISC-V generic counter"
> > +  },
> > +  {
> > +    "PublicDescription": "CPU Time",
> > +      "EventCode": "0x01",
> > +      "EventName": "riscv_time",
> > +      "BriefDescription": "CPU time RISC-V generic counter"
> > +  },
> > +  {
> > +    "PublicDescription": "CPU Instructions",
> > +      "EventCode": "0x02",
> > +      "EventName": "riscv_instret",
> > +      "BriefDescription": "CPU retired instructions RISC-V generic
> > counter"
> > +  }
> > +]
> > \ No newline at end of file =20
>=20