Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Wed, 8 Jun 2022 12:39:49 -0700
From:   Ira Weiny <ira.weiny@intel.com>
To:     Ben Widawsky <bwidawsk@kernel.org>
CC:     Dan Williams <dan.j.williams@intel.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Jonathan Cameron <Jonathan.Cameron@huawei.com>,
        Alison Schofield <alison.schofield@intel.com>,
        Vishal Verma <vishal.l.verma@intel.com>,
        Dave Jiang <dave.jiang@intel.com>,
        <linux-kernel@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
        <linux-pci@vger.kernel.org>
Subject: Re: [PATCH V10 5/9] cxl/port: Find a DOE mailbox which supports CDAT
Message-ID: <YqD7BZnbK4wuN6Zm@iweiny-desk3>
References: <20220605005049.2155874-1-ira.weiny@intel.com>
 <20220605005049.2155874-6-ira.weiny@intel.com>
 <20220606174819.hhnb4jh27nxxvrdf@bwidawsk-mobl5>
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <20220606174819.hhnb4jh27nxxvrdf@bwidawsk-mobl5>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?9lPoGlNj8jSUqxKiI/qLUdUZG83RJD5Nmezs76POl09z4V9NVA3owDW+nntk?=
 =?us-ascii?Q?QDiJOyZDv7MFtSR39ktNERha4GfcEjDhFkXyCSiLblWajGggTOZLildLWGWM?=
 =?us-ascii?Q?Fas3b4rEkYM4ev0Ud0ufjoYvdW+DHFNHtTR95DFgXhN+II8LIOuJNN323vhW?=
 =?us-ascii?Q?9Fji+yFhoivvx5vCP7coD298q/AYBNsSB+0mRpi0/RyrPuNyYZRYGGuxHb2b?=
 =?us-ascii?Q?NcZIXy6FXTEF0yAAqO9WooGlMZCKeQu8sD+2MF89f0oxMSggdeKJiXy2S5B+?=
 =?us-ascii?Q?KERsZ1PEBH6YswLGN1LuCkE3Ft+MWOMHg9sN57c01UvWFzrFMut1dMEDDa1c?=
 =?us-ascii?Q?PLLnMmcouGD/AiR/kfO8GhpunwNwg6nRJRsNtP9mI1qzrJwmjQ/IMMJkrSaK?=
 =?us-ascii?Q?wOTHx4HdtZnXtqiQIPmbV/De7Xqe3FXIWh/Pgr4jRQSoCqkWTS4eGaxrqUR6?=
 =?us-ascii?Q?flroqAdDLevY67NSszbMZJR9oVALKUE3w8t0eTVqJJ+sNlyqIiMmqxqhuKfb?=
 =?us-ascii?Q?uwsGkcwGRJMum0lRJZO3UONzNmm4Za9BOZZlej9F6TB7ju2pOF6U4B1rUAfk?=
 =?us-ascii?Q?0vj4K/homjGC6A1jN5fwCM1+O4aTVkrfjGFdyz8KYBOzKbCHyJHLy/anx/EZ?=
 =?us-ascii?Q?GmnMR0txpUGPh+EdZFiT+QjTLsOFpNUe76LtRU+L9YYp7bNHLpd4vb/VOW/I?=
 =?us-ascii?Q?MS35S4APsLRfmucS946jybcnWW8OgY3IcHQK3ZDg7JQKjEOZIkRa1j64gAZg?=
 =?us-ascii?Q?j5gsHREhQLvh1anPnvGc9Pgwd4WVeoec0bPjXI35PPJd2oqx/ZaUwKTn0ior?=
 =?us-ascii?Q?wOMO2qKTKXjFnBx7U2rNi0DvkKLMTN68wOLvOSraD10/iZattvYHkMCYJAaU?=
 =?us-ascii?Q?sRjKQSXSxObQT7dTHkDqsONyDkqWYBAPQohMzxn9DWbqdTDVVgcB8bM4aFCP?=
 =?us-ascii?Q?zJKx2JTOdUzsWQOn4NAHylPcBzpDTX/NeqM4ltz9IGOKmYT4q2y0n+IiNLZN?=
 =?us-ascii?Q?Nab5lH9EfirNbIuI19NI5BTC4y799mKnNLNlh2CbuOFxoR8xn2yP4NDu/uHl?=
 =?us-ascii?Q?IePfZ04jDPazd+G+3PIZKlIJaBjGV7pzgHYdIKPu0zlEf88OFNEKqwif+Wya?=
 =?us-ascii?Q?6oGI7eDov9Eap9kcmBYvY880TjUw2o8XWlI/nDHps0ifHWHt14YCWhZYr7Bj?=
 =?us-ascii?Q?KH5D0mBLmEhqPUtNi6govxp+Q4CsBrubJXTGykterRakqu5pzKVR9f7XEtMT?=
 =?us-ascii?Q?cV/zGMC4aQGH/rjLdNOCfdmb8cRvqxZvs8uTQCtrN/nR7Q2UV2PvpfbY4CPD?=
 =?us-ascii?Q?BpdcQIp8L77yqTgnPVeVH0WO3m7fNKy1u04zY7rlqYD45kiWYKE1KW92XbAZ?=
 =?us-ascii?Q?/CqjKrO5cSzA0n1A7v0DARkoIWv5gUMztyS7qSXb8q475DTVRvrlOC9sSXtt?=
 =?us-ascii?Q?/CGa6Ot1w2e+m9eQKYOE5X6x1gqS/BmY57xM2uYdfykza133QuTp4M8hF5SE?=
 =?us-ascii?Q?CRZEX1yWiIUjGoaTOrA7HfGUOcjVHVFPt8oLyPg6bN0zLvkYOH69qIDRITSJ?=
 =?us-ascii?Q?Il2uhymGlRp3PtnELE4VaYqeN/LN84WyOQQolt/mo0r8Dfy5RLC/F1u8OHkH?=
 =?us-ascii?Q?dc++p+yBzIeEPQKXIQyvJxGRAX/F5YINv8sbgEAYpgVroWWnKrkMVJVSJm1X?=
 =?us-ascii?Q?2e51Efqqu/qq5Qom01xxa1BkPZwEDJqc82G4GKF/sFoqxd4LNvXLXeI2xOaG?=
 =?us-ascii?Q?3H/6w6AxXQ=3D=3D?=
X-MS-Exchange-CrossTenant-Network-Message-Id: 0df5f12e-2b20-469b-16c1-08da4986b4ed
X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB6311.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2022 19:40:13.7071
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: A4rcf2m8WZ75wOaxG9tTvME8y74zKkGbG2P2LzC0TuiCjy2E4MQV1D8D5OU57MN5V1nSpDPC5B+3E+vBbSH7FA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR11MB5300
X-OriginatorOrg: intel.com
X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
        DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,
        RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,
        T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Jun 06, 2022 at 10:48:19AM -0700, Ben Widawsky wrote:
> On 22-06-04 17:50:45, ira.weiny@intel.com wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> > 
> > Each CXL device may have multiple DOE mailbox capabilities and each
> > mailbox may support multiple protocols.  CXL port devices need to query
> > the CDAT information specifically.
> > 
> > Search the DOE mailboxes for one which supports the CDAT protocol.
> > Cache that mailbox to be used for future queries.
> > 
> > Only support memory devices at this time.
> > 
> > Cc: Ben Widawsky <ben.widawsky@intel.com>
> > Cc: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > 
> > ---
> > Changes from V9
> > 	Ben Widawsky
> > 		s/cxl_find_cdat_mb/cxl_cache_cdat_mb/; add kdoc
> > 	Jonathan Cameron
> > 		Move cache_cdat to port probe [Not 100% necessary but it
> > 		goes along with reading the cdat data.]
> > 
> > Changes from V8
> > 	Incorporate feedback from Jonathan
> > 	Move all this to the cxl_port object
> > 
> > Changes from V7
> > 	Minor code clean ups
> > 
> > Changes from V6
> > 	Adjust for aux devices being a CXL only concept
> > 	Update commit msg.
> > 	Ensure devices iterated by auxiliary_find_device() are checked
> > 		to be DOE devices prior to checking for the CDAT
> > 		protocol
> > 	From Ben
> > 		Ensure reference from auxiliary_find_device() is dropped
> > ---
> >  drivers/cxl/core/pci.c | 35 +++++++++++++++++++++++++++++++++++
> >  drivers/cxl/cxl.h      |  2 ++
> >  drivers/cxl/cxlpci.h   |  1 +
> >  drivers/cxl/port.c     |  2 ++
> >  4 files changed, 40 insertions(+)
> > 
> > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> > index c4c99ff7b55e..d814d8317975 100644
> > --- a/drivers/cxl/core/pci.c
> > +++ b/drivers/cxl/core/pci.c
> > @@ -4,11 +4,14 @@
> >  #include <linux/device.h>
> >  #include <linux/delay.h>
> >  #include <linux/pci.h>
> > +#include <linux/pci-doe.h>
> >  #include <cxlpci.h>
> >  #include <cxlmem.h>
> >  #include <cxl.h>
> >  #include "core.h"
> >  
> > +#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
> > +
> >  /**
> >   * DOC: cxl core pci
> >   *
> > @@ -458,3 +461,35 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
> >  	return 0;
> >  }
> >  EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
> > +
> > +/**
> > + * cxl_cache_cdat_mb() -- cache the DOE mailbox which suports the CDAT protocol
> > + *
> > + * @port: Port to containing DOE Mailboxes
> > + *
> > + * Cache a pointer to the doe mailbox which supports CDAT.
> > + */
> > +void cxl_cache_cdat_mb(struct cxl_port *port)
> > +{
> > +	struct device *dev = port->uport;
> > +	struct cxl_memdev *cxlmd;
> > +	struct cxl_dev_state *cxlds;
> > +	int i;
> > +
> > +	if (!is_cxl_memdev(dev))
> > +		return;
> > +
> > +	cxlmd = to_cxl_memdev(dev);
> > +	cxlds = cxlmd->cxlds;
> > +
> > +	for (i = 0; i < cxlds->num_mbs; i++) {
> > +		struct pci_doe_mb *cur = cxlds->doe_mbs[i];
> > +
> > +		if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL,
> > +					  CXL_DOE_PROTOCOL_TABLE_ACCESS)) {
> > +			port->cdat_mb = cur;
> 
> What happens if cxl_pci is unloaded after this? Would it be better to copy out
> the CDAT info? Otherwise, I think you need to hold a ref on the PCI device
> (though I only took a quick look).

<sigh> I thought that could not happen but I see I was wrong.

A reference will need to be taken for at least the duration of the query.
Originally I had this set up to try and make it easier to query later.  But I
think that is a waste ATM.

I'm going to rework this ownership.

Thanks for the review,
Ira

> 
> > +			return;
> > +		}
> > +	}
> > +}
> > +EXPORT_SYMBOL_NS_GPL(cxl_cache_cdat_mb, CXL);
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index 140dc3278cde..0a86be589ffc 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -267,6 +267,7 @@ struct cxl_nvdimm {
> >   * @component_reg_phys: component register capability base address (optional)
> >   * @dead: last ep has been removed, force port re-creation
> >   * @depth: How deep this port is relative to the root. depth 0 is the root.
> > + * @cdat_mb: Mailbox which supports the CDAT protocol
> >   */
> >  struct cxl_port {
> >  	struct device dev;
> > @@ -278,6 +279,7 @@ struct cxl_port {
> >  	resource_size_t component_reg_phys;
> >  	bool dead;
> >  	unsigned int depth;
> > +	struct pci_doe_mb *cdat_mb;
> >  };
> >  
> >  /**
> > diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> > index fce1c11729c2..ddbb8b77752e 100644
> > --- a/drivers/cxl/cxlpci.h
> > +++ b/drivers/cxl/cxlpci.h
> > @@ -74,4 +74,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
> >  int devm_cxl_port_enumerate_dports(struct cxl_port *port);
> >  struct cxl_dev_state;
> >  int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
> > +void cxl_cache_cdat_mb(struct cxl_port *port);
> >  #endif /* __CXL_PCI_H__ */
> > diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> > index 3cf308f114c4..04f3d1fc6e07 100644
> > --- a/drivers/cxl/port.c
> > +++ b/drivers/cxl/port.c
> > @@ -49,6 +49,8 @@ static int cxl_port_probe(struct device *dev)
> >  	if (IS_ERR(cxlhdm))
> >  		return PTR_ERR(cxlhdm);
> >  
> > +	cxl_cache_cdat_mb(port);
> > +
> >  	if (is_cxl_endpoint(port)) {
> >  		struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
> >  		struct cxl_dev_state *cxlds = cxlmd->cxlds;
> > -- 
> > 2.35.1
> >